Vivado：TCL命令将clock1和clock2之间的时序路径设置为错误路径（TIMING-6和TIMING-7）

Question

让我们假设我有一个具有两个时钟域的FPGA / VHDL设计，并且一个时钟域到另一个时钟域之间的每条路径都以VHDL编写了CDC同步代码，以确保在交叉之间传递信息时没有元稳定性。时钟边界。

在这种情况下，Vivado TCL命令将Clock1和Clock2之间的时序路径设置为false路径是什么？

示例编译器警告：

WARNING: [TIMING-6] The clocks clk_1 and clk_2 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_fpga_0] -to [get_clocks clk_out1_design_zynq_zyboz720_clk_wiz_0_0] 

WARNING: [TIMING-7] The clocks clk_1 and clk_2 are related (timed together) but they have no common node. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_1] -to [get_clocks clk_2]

Answer 1

set_false_path -from [get_clocks clk_1] -to [get_clocks clk_2]

此命令将删除您的警告以及与该CDC相关的预期严重警告“未达到定时”，但这不能确保您的设计正常运行。

我建议您还在重新同步信号上添加属性ASYNC_REG，以确保合成器将2 CDC FF放置得非常近（如果可能在同一片中）：

attribute ASYNC_REG : string;
attribute ASYNC_REG of a_r_clk_2  : signal is "TRUE"; -- Output of the first resync FF in clk_2
attribute ASYNC_REG of a_rr_clk_2 : signal is "TRUE"; -- Output of the second resync FF in clk_2