Question

我正在尝试从vhdl中的自然数中减去，但是我不明白该怎么做，有人对我可以在代码中更改的内容有任何想法吗？我的问题是，我无法弄清楚我可以进行哪些更改，以使cnt降为1直到1变为零。

library ieee;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_1164.all; 

entity dsf_monostable is
  port (
    aclear  : in  bit;
    data    : in  natural range 0 to 255;
    trigger : in  bit;
    clk     : in  bit;
    q       : out bit
  );
end dsf_monostable;

architecture monostable_arc of dsf_monostable is
  signal cnt : natural range 0 to 255 := 0;
begin
  process (aclear, trigger, cnt)
  begin

    if (aclear = '1') then 
      cnt <= 0;  

    elsif (trigger = '1' and cnt = 0) then
      cnt <= data;
    end if;
  end process;

  process (clk, cnt)
  begin
    if ((clk'event and clk = '1') and cnt /= 0) then
      cnt <= cnt - 1;
    end if;
  end process;

  q <= '0' when (cnt=0 or aclear='1') 
           else '1';
end monostable_arc;

对于bit_vector

architecture timer_arc of dsf_timer is
  signal cnt : bit_vector (7 downto 0);

begin
process (clk)
  begin
    if ((clk'event and clk = '1') and (cnt > "00000000")) then
    cnt <= cnt - "00000001"
     end if;
  end process;

我希望，当rise_clk发生时，cnt会递减1

VHDL-尝试从自然和bit_vector中减去

0 个答案: