Question

我正在尝试从Modelsim中的chipverify网站运行一些代码，但是它不起作用-我也不知道为什么。网站上的示例与wait_order有关。

module tb;
  // Declare three events that can be triggered separately
  event a, b, c;

  // This block triggers each event one by one
  initial begin
    #10 -> a;
    #10 -> b;
    #10 -> c;
  end

  // This block waits until each event is triggered in the given order
  initial begin

    wait_order (a,b,c) 
      $display ("Events were executed in the correct order");
    else 
        $display ("Events were NOT executed in the correct order !");  
  end
endmodule

我希望输出：

Events were executed in the correct order.

但是我发现这样的东西：

syntax error, unexpected "SystemVerilog keyword 'wait_order'"

Answer 1

这是Modelsim中SystemVerilog的未实现功能。检查文档。

带有断言的

SystemVerilog sequence可以为您提供许多相同的功能。

Modelsim中的wait_order问题-意外关键字

1 个答案: