Load-use penalty
● Assume that the processor is equipped with bypasses eliminating
the „classic” R-A-W hazard
● Consider the following sequence
lw $4, ....
add $6, $5, $4
This time the R-A-W hazard results from memory load instruction
Data read from memory is not available until MEM stage
The bypass from ALU stage will NOT contain the proper data
Bypasses may reduce this problem but not eliminate it
Memory data from MEM stage may be passed to RD using a bypass
While the 2nd
instruction is in RD, the load instruction is in ALU, not in
MEM
● The problem is called Load-Use penalty
这是我班上的演讲幻灯片。
“加重使用罚金”一词是否还有其他名称吗？
我不是通过搜索in google来找到它的。