Question

module fronter ( arc, length, clinic ) ;
 input [7:0] arc;
 output reg [7:0] length ;

 input [1:0] clinic;
 input en0, en1, en2, en3; // 11

 // clock generator  is here

 g_cal A( en0) ;
 g_cal B( en1) ;
 g_cal C( en2) ;
 g_cal D( en3) ;

always @( negedge arc, posedge clk )
  case ( clinic ) 
    2'b00 : { en3, en2, en1, en0 } = 4'b0001;    // 23
    2'b01 : { en3, en2, en1, en0 } = 4'b0010;    // 24
    2'b10 : { en3, en2, en1, en0 } = 4'b0100;    // 25
    2'b11 : { en3, en2, en1, en0 } = 4'b1000;    // 26
    default : { en3, en2, en1, en0 } = 4'bxxxx;  // 27
  endcase

// I am trying to change value of en to call corresponding intance with that 
//corresponding en value

endmodule

module g_cal ( en ) ;

 input en ;
 // some other jobs, calling another instances after making some job

endmodule

编译时，编译器给我;

verilog.v:23: error: en0 is not a valid l-value in Numerator.
verilog.v:11:      : en0 is declared here as wire.
verilog.v:24: error: en1 is not a valid l-value in Numerator.
verilog.v:11:      : en1 is declared here as wire.
verilog.v:25: error: en2 is not a valid l-value in Numerator.
verilog.v:11:      : en2 is declared here as wire.
verilog.v:26: error: en3 is not a valid l-value in Numerator.
verilog.v:11:      : en3 is declared here as wire.
verilog.v:27: error: en3 is not a valid l-value in Numerator.
verilog.v:11:      : en3 is declared here as wire.
segmentation fault

我该如何解决？ 为什么会出错？

编辑：我已经解决了问题;

   // I erased that line "input en0, en1, en2, en3; // 11"

 // clock generator  is here

 g_cal A(  1'b0) ;
 g_cal B(  1'b0) ;
 g_cal C(  1'b0) ;
 g_cal D(  1'b0) ;

always @( negedge arc, posedge clk )
/* erasing all those line 
 case ( clinic ) 
    2'b00 : { en3, en2, en1, en0 } = 4'b0001;    // 23
    2'b01 : { en3, en2, en1, en0 } = 4'b0010;    // 24
    2'b10 : { en3, en2, en1, en0 } = 4'b0100;    // 25
    2'b11 : { en3, en2, en1, en0 } = 4'b1000;    // 26
    default : { en3, en2, en1, en0 } = 4'bxxxx;  // 27
  endcase

我将使用if和else结构，并使用1'b1 * /

调用相应的实例

 // I am trying to change value of en to call corresponding intance with that 
//corresponding en value

endmodule

Answer 1

您正在尝试分配input（这很糟糕）。将input en0, en1, en2, en3;更改为output reg en0, en1, en2, en3;。由于您要在程序块（即reg或always）内分配该变量，因此initial是必需的。 “非有效的l值”消息试图告诉你这个。

另外，我假设11,23,24等是复制粘贴中的杂散行号...

Answer 2

写作时问题已解决;

reg en0, en1, en2, en3 ;

initial begin 
  en0 <= 1'b0; en1 <= 1'b0; 
  en2 <= 1'b0; en3 <= 1'b0;
end

g_cal A(  en0) ;
g_cal B(  en1) ;
g_cal C(  en2) ;
g_cal D(  en3) ;

@Marty强调了重要的事情“因为你在程序块中分配给那个变量（即，总是或初始的），所以reg是必要的。”

不是有效的l值 - verilog编译器错误

2 个答案: