如何根据利用率比较两个电路

时间:2019-05-28 23:25:46

标签: vhdl fpga xilinx vivado

我需要综合一些硬件IP。 IP包含几个我可以使用的通用参数。综合和实现后,每种参数组合给我提供了不同的利用率报告。

因此,例如对于两种不同的配置Design_1Design_2,我在Vivado 2018.1中得到以下内容。第三行是Design_2的值与Design_1的值之比。

因此,在这个简单的示例中您可以看到,Design_2的Slice LUT较少,而F7 Muxes略多。

我的问题是如何得出每个成本的结论?我应该给Slice LUT或寄存器...等特权吗?

+----------+-------------------+-----------------+------------------+----------+-------------------+-------------------+---------------+---------------------+----------------+------+------------+--------------+-------------+------------+----------+---------+------------+---------+---------------------------+-------------------------+-----------------------------+--------+--------+----------+---------+------------+-----------+---------+--------+---------+---------+-----------+----------+-----------+-------------+---------+----------+-----------+---------+
|   Name   |    Slice LUTs     | Slice Registers |     F7 Muxes     | F8 Muxes |       Slice       |   LUT as Logic    | LUT as Memory | LUT Flip Flop Pairs | Block RAM Tile | DSPs | Bonded IOB | Bonded IPADs | PHY_CONTROL | PHASER_REF | OUT_FIFO | IN_FIFO | IDELAYCTRL | IBUFDS  | PHASER_OUT/PHASER_OUT_PHY | PHASER_IN/PHASER_IN_PHY | IDELAYE2/IDELAYE2_FINEDELAY | ILOGIC | OLOGIC | BUFGCTRL |  BUFIO  | MMCME2_ADV | PLLE2_ADV | BUFMRCE | BUFHCE |  BUFR   | BSCANE2 | CAPTUREE2 | DNA_PORT | EFUSE_USR | FRAME_ECCE2 | ICAPE2  | PCIE_2_1 | STARTUPE2 |  XADC   |
+----------+-------------------+-----------------+------------------+----------+-------------------+-------------------+---------------+---------------------+----------------+------+------------+--------------+-------------+------------+----------+---------+------------+---------+---------------------------+-------------------------+-----------------------------+--------+--------+----------+---------+------------+-----------+---------+--------+---------+---------+-----------+----------+-----------+-------------+---------+----------+-----------+---------+
| Design_1 |             34124 |           16913 |             1453 |       91 |             10272 |             31538 |          2586 |                9020 |             37 |   11 |        125 | 0            |           1 |          1 |        4 |       2 |          1 | 0       |                         4 |                       2 |                          16 |     16 |     46 |       10 | 0       |          2 |         2 | 0       |      2 | 0       |       4 | 0         | 0        | 0         | 0           | 0       | 0        | 0         | 0       |
| Design_2 |             34097 |           16913 |             1550 |       91 |             10189 |             31511 |          2586 |                9021 |             37 |   11 |        125 | 0            |           1 |          1 |        4 |       2 |          1 | 0       |                         4 |                       2 |                          16 |     16 |     46 |       10 | 0       |          2 |         2 | 0       |      2 | 0       |       4 | 0         | 0        | 0         | 0           | 0       | 0        | 0         | 0       |
| -------- |                   |                 |                  |          |                   |                   |               |                     |                |      |            |              |             |            |          |         |            |         |                           |                         |                             |        |        |          |         |            |           |         |        |         |         |           |          |           |             |         |          |           |         |
| (2)/(1)  | 0.999208768022506 |               1 | 1.06675843083276 |        1 | 0.991919781931464 | 0.999143889910584 |             1 |    1.00011086474501 |              1 |    1 |          1 | #DIV/0!      |           1 |          1 |        1 |       1 |          1 | #DIV/0! |                         1 |                       1 |                           1 |      1 |      1 |        1 | #DIV/0! |          1 |         1 | #DIV/0! |      1 | #DIV/0! |       1 | #DIV/0!   | #DIV/0!  | #DIV/0!   | #DIV/0!     | #DIV/0! | #DIV/0!  | #DIV/0!   | #DIV/0! |
+----------+-------------------+-----------------+------------------+----------+-------------------+-------------------+---------------+---------------------+----------------+------+------------+--------------+-------------+------------+----------+---------+------------+---------+---------------------------+-------------------------+-----------------------------+--------+--------+----------+---------+------------+-----------+---------+--------+---------+---------+-----------+----------+-----------+-------------+---------+----------+-----------+---------+

1 个答案:

答案 0 :(得分:2)

这取决于您的需求, LUT F7多路复用器是您FPGA中不同的物理单元。因此,即使您不使用它,它也会在那里。

如果您拥有一个比另一个资源更为关键的资源,则应尝试将关键资源的利用率降至最低,以简化布局和布线。

如果没有什么要紧的地方,我认为最好先使用 F7多路复用器,因为 Slice LUT 对于其余的设计更灵活。