我有一个设计，将锁存器作为存储器来存储数据缓冲区。如何在设计编译器中限制它并分析时序？封闭的正确标准是什么？
我正在使用标准的report_timing，但是该报告看起来不正确。
锁存器用于创建深度为100个元素的FIFO，以节省面积。这里简化为两个元素。
test_latch.sdc
read_verilog test_latch.sv
create_clock -period 10 -name clk [get_ports clk]
set_input_delay 5 -clock [get_clocks clk] [all_inputs]
set_output_delay 5 -clock [get_clocks clk] [all_outputs]
dc_shell> report_timing
Information: Updating design information... (UID-85)
****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : test_latch
****************************************
Operating Conditions: Library:
Wire Load Model Mode: enclosed
Startpoint: latch_Xin0_reg[1]
(positive level-sensitive latch clocked by clk)
Endpoint: latch_Xin_reg[7]
(positive level-sensitive latch clocked by clk)
Path Group: clk
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
test_latch ZeroWLM
Point Incr Path
--------------------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
time given to startpoint 0.04 0.04
latch_Xin0_reg[1]/D (LDP_1) 0.00 0.04 r
latch_Xin0_reg[1]/Q (LDP_1) 0.04 0.08 r
U24/X (ND2_1) 0.01 0.09 f
U26/X (ND2_1) 0.01 0.10 r
U27/X (ND3_0P5) 0.01 0.12 f
U28/X (INV_1) 0.01 0.13 r
U33/X (AN2_0P5) 0.02 0.15 r
U32/X (EO2_0P5) 0.02 0.16 r
latch_Xin_reg[7]/D (LDP_1) 0.00 0.16 r
data arrival time 0.16
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
latch_Xin_reg[7]/G (LDP_1) 0.00 0.00 r
time borrowed from endpoint 0.16 0.16
data required time 0.16
--------------------------------------------------------------------------
data required time 0.16
data arrival time -0.16
--------------------------------------------------------------------------
slack (MET) 0.00
Time Borrowing Information
--------------------------------------------------------------
clk nominal pulse width 5.00
library setup time -0.03
--------------------------------------------------------------
max time borrow 4.97
actual time borrow 0.16
--------------------------------------------------------------
module test_latch(
input clk, rstn,
input pop, push,
input signed [7:0] Xin,
output wire [7:0] Yout
);
reg [7:0] reg_Xin;
reg [7:0] latch_Xin0;
reg [7:0] latch_Xin;
reg [7:0] reg_Yout;
always @(posedge clk or negedge rstn)
if(!rstn)
reg_Xin <= 'd0;
else
reg_Xin <= Xin[7:2] * Xin[1:0];
always @(*)
if(clk)
begin
latch_Xin0 <= reg_Xin;
latch_Xin <= latch_Xin0 + 8'd10;
end
always @(posedge clk or negedge rstn)
if(!rstn)
reg_Yout <= 'd0;
else
reg_Yout <= latch_Xin[7:4] * latch_Xin[3:0];
assign Yout = reg_Yout;
endmodule