JK触发器代码:
T
计数器代码:
Class.cast
测试平台代码:
library ieee;
use ieee.std_logic_1164.all;
ENTITY JK IS PORT
(
J,K,clk,rst,set : IN std_logic;
Q, nQ : OUT std_logic
);
END JK;
ARCHITECTURE arch OF JK IS
SIGNAL Qtemp : std_logic := '0';
SIGNAL nQtemp : std_logic := '1';
BEGIN
Q <= Qtemp;
nQ <= nQtemp;
jk_process : PROCESS(clk,rst,set)
BEGIN
if(rst = '1') then
Qtemp <= '0';
nQtemp <= '1';
elsif(set = '1') then
Qtemp <= '1';
nQtemp <= '0';
elsif(clk'event and clk = '1') then
if(J = '0' and K = '0') then
NULL;
elsif(J = '1' and K = '0') then
Qtemp <= '1';
nQtemp <= '0';
elsif(J = '0' and K = '1') then
Qtemp <= '0';
nQtemp <= '1';
elsif(J = '1' and K = '1') then
Qtemp <= not Qtemp;
nQtemp <= not nQtemp;
end if;
end if;
END PROCESS;
END arch;
我有两个无法解决的问题:
有趣的是,当我在所有JK触发器上将0强制设为rst输入时,and开始正常工作,并且library ieee;
use ieee.std_logic_1164.all;
ENTITY brojilo IS PORT
(
clk : IN std_logic;
Q_vector : OUT std_logic_vector(3 downto 0) := "0000";
Q_negated_vector : OUT std_logic_vector(3 downto 0) := "0000";
and_in_values : OUT std_logic_vector(3 downto 0) := "0000";
and_out_value : OUT std_logic := '0'
);
END brojilo;
ARCHITECTURE arch OF brojilo IS
SIGNAL int_clk_b0_b1 : std_logic := '0';
SIGNAL int_clk_b1_b2 : std_logic := '0';
SIGNAL int_clk_b2_b3 : std_logic := '0';
SIGNAL Q_temp_vector : std_logic_vector(3 downto 0) := "0000";
SIGNAL Q_temp_negated_vector : std_logic_vector(3 downto 0) := "0000";
SIGNAL and_vector : std_logic_vector(3 downto 0) := "0000";
SIGNAL and_out_reset : std_logic := '0';
BEGIN
and_out_reset <= and_vector(0) and and_vector(1) and and_vector(2) and and_vector(3);
and_out_value <= and_out_reset;
b0 : ENTITY work.JK port map(J => '1', K => '1', clk => clk, rst => and_out_reset, set => '0', Q => Q_temp_vector(0), nQ => Q_temp_negated_vector(0));
int_clk_b0_b1 <= Q_temp_negated_vector(0);
b1 : ENTITY work.JK port map(J => '1', K => '1', clk => int_clk_b0_b1, rst => and_out_reset, set => '0', Q => Q_temp_vector(1), nQ => Q_temp_negated_vector(1));
int_clk_b1_b2 <= Q_temp_negated_vector(1);
b2 : ENTITY work.JK port map(J => '1', K => '1', clk => int_clk_b1_b2, rst => and_out_reset, set => '0', Q => Q_temp_vector(2), nQ => Q_temp_negated_vector(2));
int_clk_b2_b3 <= Q_temp_negated_vector(2);
b3 : ENTITY work.JK port map(J => '1', K => '1', clk => int_clk_b2_b3, rst => and_out_reset, set => '0', Q => Q_temp_vector(3), nQ => Q_temp_negated_vector(3));
and_vector(0) <= Q_temp_negated_vector(0);
and_vector(1) <= Q_temp_vector(1);
and_vector(2) <= Q_temp_negated_vector(2);
and_vector(3) <= Q_temp_vector(3);
and_in_values <= and_vector;
Q_vector <= Q_temp_vector;
Q_negated_vector <= Q_temp_negated_vector;
END arch;
输出行在1010上触发1。