断言失败错误尝试使用Icarus编译SV文件

时间:2019-05-09 10:48:06

标签: verilog system-verilog iverilog icarus

我尝试使用Icarus编译带有其测试平台的mux.sv设计模块,但是出现以下错误vvp: array.cc:906: void compile_var2_array(char*, char*, int, int, int, int, bool): Assertion `0' failed. Aborted (core dumped)

下面是测试平台的代码段

`include "mux.sv"
module tb_mux();

    bit a0, a1, a2, d0, d1, d2, d3, d4, d5, d6, d7, out;
    // read
    bit expectedOutput;

    int passedFile;
    integer i;
    bit [11:0] testvector[2047:0];

    // design unit under test instantiation
    mux dut(.out(out), .a0(a0), .a1(a1), .a2(a2), .d0(d0), .d1(d1), .d2(d2), .d3(d3), .d4(d4), .d5(d5), .d6(d6), .d7(d7));
initial begin
            $readmemb("testcases", testvector);
            passedFile = $fopen("passed.txt", "w");
            if(passedFile)
                $display("file opened");
            else
                $display("couldn't open the file");
end

task assertOutput;
    begin
    int unsigned cases = 0;
    for (i = 0; i< 2048; i++)begin
        {a0, a1, a2, d0, d1, d2, d3, d4, d5, d6, d7, expectedOutput} = testvector[i];

       #10;
           if(a0 == 1'b0 && a1 == 1'b0 && a2 == 1'b0 && out == expectedOutput)
                cases = cases + 1;

           else if(a0 == 1'b0 && a1 == 1'b0 && a2 == 1'b1 && out == expectedOutput)
               cases = cases + 1;

           else if(a0 == 1'b0 && a1 == 1'b1 && a2 == 1'b0 && out == expectedOutput)
               cases = cases + 1;

           else  $display(0);
    end
    $fdisplay(passedFile, "%d", cases);
end
endtask

endmodule

我的测试台可能会发生什么错误,以产生此错误?

1 个答案:

答案 0 :(得分:0)

我必须将位数据类型更改为逻辑,以使其可以与伊卡洛斯一起使用。