Question

我正在尝试在VHDL中实现FSM以模拟交通信号灯控制器。我有一些问题。我想我需要一个时钟信号来执行此操作，但是我不知道该怎么做。如何在约束文件中定义时钟，以及如何在主代码中使用它？我想我想使用3hz的时钟，但是我愿意接受其他建议，因为我的目标是各州之间的3秒延迟。另外，如何使用该时钟在每个状态之间创建3秒的延迟？我在下面提供了一个示例，说明当前代码以及约束文件的相关部分。

entity TrafficController is
  Port ( 
        clk, rst: in std_logic;
        car_ew, car_ns: in std_logic;
        LED: out std_logic_vector (5 downto 0) := "100001"; --total of 6 LED for the traffic lights
        LED2: out std_logic_vector (5 downto 0) := "100001" --for the second set of lights just double up the code below i think
  );
end TrafficController;

architecture Tcontroller of TrafficController is
type states is 
    (s0, s1, s2); --one state for each configuration of the LED
signal state_current, state_next: states;

signal count: STD_LOGIC_VECTOR (3 downto 0);
constant sec1: STD_LOGIC_VECTOR (3 downto 0) := "0011";

begin 

--basic reset to initial state logic (process)
process (rst,clk) 

begin
       if (rst = '1') then
           state_current <= s0;
           count <= "0000";
       elsif (clk'event and clk = '1') then
           state_current <= state_next;
       end if;
end process;

--next state logic (process 2)
process (state_current, car_ew, car_ns)

begin
       case state_current is
            when s0 => --initial state, green for NS, red for EW
                if car_ew = '0' then
                    state_next <= s0;
                else
                    if count < sec1 then
                        state_next <= s0;
                        count <= count + 1;
                    else
                        state_next <= s1;
                        count <= "0000";
                    end if;
                end if;
            when s1 => --Yellow NS, Red EW
                if count < sec1 then
                    state_next <= s1;
                    count <= count + 1;
                else
                    state_next <= s2;
                    count <= "0000";
                end if;
            when s2 => --Both red
                if count < sec1 then
                    state_next <= s2;
                    count <= count + 1;
                else
                    state_next <= s0;
                    count <= "0000";
                end if;
        end case;
end process;

--Moore output logic (process 3)
process(state_current)

begin
LED <= "100001"; --initial state of LED
LED2 <= "100001"; --second set of lights
    case state_current is
        when s0 =>
            LED <= "100001";
            LED2 <= "100001";
        when s1 =>
            LED <= "010001";
            LED2 <= "010001";
        when s2 =>
            LED <= "001001";
            LED2 <= "001001";
        when s3 =>
            LED <= "001100";
            LED2 <= "001100";
        when s4 =>
            LED <= "001010";
            LED2 <= "001010";
        when s5 => 
            LED <= "001001";
            LED2 <= "001001";
     end case;
end process;
end Tcontroller;

## Clock signal
#set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk}];

#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets { clk }];

FSM我需要时钟吗？如何实现状态之间的延迟？

0 个答案: