我正在尝试使用OpenMP执行程序,并查看执行时间,但我不断出现Floating-point-exception。
没有design.cpp文件,我将无法在测试台上实例化DUT。因此将该文件包含在其他CPP中。
我能够在没有OpenMP的情况下运行此文件。
关于我在哪里实施错误的任何帮助。
#include "systemc.h"
#include "design.cpp"
#include "omp.h"
int sc_main(int argc, char * argv[]) {
sc_signal < bool > clock;
sc_signal < bool > reset;
sc_signal < bool > enable;
sc_signal < sc_uint < 4 > > counter_out;
int i = 0;
// Connect the DUT
first_counter counter("COUNTER");
counter.clock(clock);
counter.reset(reset);
counter.enable(enable);
counter.counter_out(counter_out);
sc_start(1, SC_NS);
// Open VCD file
sc_trace_file * wf = sc_create_vcd_trace_file("counter");
// Dump the desired signals
sc_trace(wf, clock, "clock");
sc_trace(wf, reset, "reset");
sc_trace(wf, enable, "enable");
sc_trace(wf, counter_out, "count");
// Initialize all variables
reset = 0; // initial value of reset
enable = 0; // initial value of enable
#pragma omp parallel default (none) shared(i, reset, enable, clock, cout, wf, counter_out)
{
# pragma omp for // pragma
for (i = 0; i < 5; i++) {
clock = 0;
sc_start(1, SC_NS);
clock = 1;
sc_start(1, SC_NS);
}
reset = 1; // Assert the reset
cout << "@" << sc_time_stamp() << " Asserting reset\n" << endl;
# pragma omp for
for (i = 0; i < 10; i++) {
clock = 0;
sc_start(1, SC_NS);
clock = 1;
sc_start(1, SC_NS);
}
reset = 0; // De-assert the reset
cout << "@" << sc_time_stamp() << " De-Asserting reset\n" << endl;
# pragma omp for
for (i = 0; i < 5; i++) {
clock = 0;
sc_start(1, SC_NS);
clock = 1;
sc_start(1, SC_NS);
}
cout << "@" << sc_time_stamp() << " Asserting Enable\n" << endl;
enable = 1; // Assert enable
# pragma omp for
for (i = 0; i < 20; i++) {
clock = 0;
sc_start(1, SC_NS);
clock = 1;
sc_start(1, SC_NS);
}
}
cout << "@" << sc_time_stamp() << " De-Asserting Enable\n" << endl;
enable = 0; // De-assert enable
cout << "@" << sc_time_stamp() << " Terminating simulation\n" << endl;
sc_close_vcd_trace_file(wf);
return 0; // Terminate simulation
}
// design.cpp
#include "systemc.h"
SC_MODULE(first_counter) {
sc_in_clk clock; // Clock input of the design
sc_in < bool > reset; // active high, synchronous Reset input
sc_in < bool > enable; // Active high enable signal for counter
sc_out < sc_uint < 4 > > counter_out; // 4 bit vector output of the
counter
//------------Local Variables Here---------------------
sc_uint < 4 > count;
//------------Code Starts Here-------------------------
// Below function implements actual counter logic
void incr_count() {
// At every rising edge of clock we check if reset is active
// If active, we load the counter output with 4'b0000
if (reset.read() == 1) {
count = 0;
counter_out.write(count);
// If enable is active, then we increment the counter
} else if (enable.read() == 1) {
count = count + 1;
counter_out.write(count);
cout << "@" << sc_time_stamp() << " :: Incremented Counter " <<
counter_out.read() << endl;
}
} // End of function incr_count
// Constructor for the counter
// Since this counter is a positive edge trigged one,
// We trigger the below block with respect to positive
// edge of the clock and also when ever reset changes state
SC_CTOR(first_counter) {
cout << "Executing new" << endl;
SC_METHOD(incr_count);
sensitive << reset;
sensitive << clock.pos();
} // End of Constructor
}; // End of Module counter