Question

我是vhdl的初学者。我写了一个有关8位加法器的代码。当我开始编译时，出现一个我不知道如何解决的错误。我的代码中可能有其他我不注意到的错误。这是我的代码：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity Adder_plus is 
  generic (size: integer :=8);
  port( x,y: in std_logic_vector(size-1 downto 0);
        sum: out std_logic_vector(size-1 downto 0);
         c_out: out std_logic );
end Adder_plus;

architecture RTL of Adder_plus is
  signal s: std_logic_vector(size downto 0);
  begin
    s <= std_logic_vector("0" & unsigned(x) + "0" & unsigned(y)); --I wrote it this way because it does not recognise "+" 
    sum <= s(size-1 downto 0);
    c_out <= s(size);
end RTL;

这是错误tha出现：

Error (10344): VHDL expression error at Adder_plus.vhd(16): expression has 17 elements, but must have 9 elements

我不知道如何解决编译错误（VHDL错误10344）

0 个答案: