Question

我正在尝试实现OCP到AXI的桥接器，以将OCP信号转换为AXI信号，以便OCP主设备可以与AXI从设备通信。但是，我对Verilog并不满意，因为我还不熟悉它，我想我还不清楚桥梁的工作原理。

我试图编写一些如下所示的代码。

目前，我对OCP到AXI桥接的想法是尽可能将OCP信号映射到AXI信号，反之亦然。我也了解桥接器需要首先接收来自OCP主设备的信号，并仅在下一个时钟周期输出AXI信号。

我可以问一下我的想法是否正确吗？

module ocp2axi_bridge (
    /* OCP signals */
    input clk,    // Clock
    //input clk_en, // Clock Enable;  unsure if required
    input [31:0] maddr, 
    input [ 2:0] mcmd, 
    input [31:0] mdata, 
    input [31:0] sdata, 
    input        mdatavalid, 
    input        mrespaccept, 
    input        mdatalast, 
    input        mdatabyteen, 
    input        sresp,
    input        sresplast,
    output       scmdaccept, 
    output       sdataaccept, 

    /* AXI Write signals */
    output [31:0] awaddr, 
    output        awvalid, 
    input         awready, 
    output [31:0] wdata, 
    output        wlast, 
    output        wvalid, 
    output [ 3:0] wstrb, 
    input         wready,  //slave can accept write data
    input         bresp,
    input         bvalid,
    output        bready,  // master can accept write response

    /* AXI Read signals */
    output [31:0] araddr, 
    output        arvalid,
    input         arready,
    input [31:0]  rdata, 
    input         rlast, 
    input         rvalid, // no mappable signal in OCP (unsure)
    output        rready, 
    input         rresp 
);

always @ (posedge clk)begin 
    if (mcmd == 3'b001) begin //write operation
        awaddr <= maddr; // converter drives AXI awaddr
        awvalid <= 1; //converter drives awvalid to elicit response from AXI slave
    end
    else if (mcmd == 3'b010) begin 
        araddr <= maddr; //converter drives AXI araddr
        arvalid <= 1; //converter drives awvalid to elicit response from AXI slave
    end
end

assign scmdaccept = awready | arready; // scmdaccept is triggered either by awready or arready HIGH
assign sdataaccept = wready; 
assign mrespaccept = bready | rready; // guess that mrespaccept is the overall sig. for master's readiness to accept slave responses

always @ (posedge clk and scmdaccept == 1) begin 
    if (mcmd == 3'b001) begin // write ops
        wdata <= mdata; // route data on mdata line to AXI wdata line
        mdatavalid <= wvalid; // channel holds valid write data
        wlast <= mdatalast; // route LAST signal to AXI wlast
        wstrb <= mdatabyteen; // route OCP lane strobe controls to AXI wstrb
    end
    else if (mcmd == 3'b010) begin 
        sdata <= rdata; //put incoming rdata from AXI slave to OCP mdata
        sresplast <= rlast; // AXI slave rlast response mapped to sresplast
    end
end

/* ^ (XOR) is used because an OKAY response is bvalid = 1 and bresp = 0 */
always@(*) begin 
    if (bvalid ^ bresp) begin 
        sresp <= 1;
    end
    else begin
        sresp <= 0;
    end
end

endmodule

感谢大家的帮助！：）

实施OCP到AXI桥

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