VHDL-函数形式参数的对象类不能为变量

Question

我试图编写一些VHDL来进行符号幅度加法（过载+），而不在代码中使用任何+。使用Quartus 2 13.0 Cyclonce IV E EP4ce115F29C7

当我尝试编译当前项目时，我得到了堆栈跟踪：

这使我指向这一行：

variable sum:std_logic_vector(max downto 0);

我不确定我要去哪里错，我一直在寻找有关此内容的资料，但找不到任何东西。

这是我的代码：

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

package SIGN_MAGNITUDE_ARITH is 
    constant word_size: positive := 32;
    type SIGN_MAG is array(natural range <>) of std_logic;
    function "+"(L:SIGN_MAG; R:SIGN_MAG;) return SIGN_MAG;
    --function "-"(L: SIGN_MAG; R: SIGN_MAG;) return SIGN_MAG;
    --function "*"(L: SIGN_MAG; R: SIGN_MAG;) return SIGN_MAG;
    --procedure "/"(signal Z, D: in SIGN_MAG; signal Q,R: out SIGN_MAG);
end;

package body SIGN_MAGNITUDE_ARITH is
    -- Sign Magnitude addition (overload "+")
    function "+"(L: SIGN_MAG; R: SIGN_MAG;) return SIGN_MAG is
        constant max = (MAX(R'length, L'length));
        variable carry:std_logic:='0';
        variable sum:std_logic_vector(max downto 0);
    begin
        if(L(L'length-1)='0') and (R(R'length-1)='0') then
            for i in 0 to max - 2 loop
                sum(i):= L(i) xor R(i) xor carry;
                carry:=( L(i) and R(i) ) or ( L(i) and carry ) or ( R(i) and carry );
            end loop;
            sum(max-1):=carry;
            sum(max):='0';
        end if;
        return sum;
    end;
end;