增加功能覆盖范围来通知信号

Question

我是系统Verilog中功能覆盖的新手。当两个信号不相等时，我想写一个封面。

例如，我对每个信号有两个单独的报道。

    covergroup group1 @(posedge `TB_TOP.clk); 
    cpb_1 : coverpoint `TB_TOP.sig1 {
        bins r_zero = {0};
        bins r_one = {1};
     endgroup
    covergroup group2 @(posedge `TB_TOP.clk); 
    cpb_2 : coverpoint `TB_TOP.sig2 {
        bins r_zero = {0};
        bins r_one = {1};
     endgroup

现在，我想在时钟posege处添加sig1不等于sig2时的另一个。 谢谢

Answer 1

您的意思是这样的吗？

covergroup group3 @(posedge `TB_TOP.clk);
  // coverpoint can take an expression, so provide sig1!=sig2
  cpb_3: coverpoint (`TB_TOP.sig1 != `TB_TOP.sig2) {
    // Since we only want to cover this case, sample a true value (1) only
    bins covered = {1};
  }
endgroup