我正在使用分频器,并且可以选择频率,但是我无法正常工作。语法检查每次都会通过,但是当我开始仿真时,会出现以下错误:“ FATAL_ERROR:Simulator:CompilerAssert.h:40:1.20-文件../src/VhdlTreeTransform.cpp中的内部编译器错误在第296行提供有关此内容的技术支持问题,请访问http://www.xilinx.com/support。”
我已经搜索了这个问题,找不到任何解决方案。我是新手,这可能是一个平庸的问题,如果您能帮助我,我将很高兴。
主要代码在这里:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity Freq4Sel is
Port ( cp : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR (1 downto 0);
outcp : buffer STD_LOGIC:= '0');
end Freq4Sel;
architecture Behavioral of Freq4Sel is
begin
process(cp)
variable selects : integer range 0 to 50000000;
variable temp: integer range 0 to 50000000 := 0;
begin
with sel select
selects := 50000000 when "11",
5000000 when "10",
2000000 when "01",
1000000 when others;
if (cp'event and cp = '1') then
temp := temp+1;
if(temp>=selects) then
outcp <= not outcp;
end if;
end if;
end process;
end Behavioral;
用于仿真测试的文件在这里:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY Freq4Sel_w IS
END Freq4Sel_w;
ARCHITECTURE behavior OF Freq4Sel_w IS
COMPONENT Freq4Sel
PORT(
cp : IN std_logic;
sel : IN std_logic_vector(1 downto 0);
outcp : BUFFER std_logic
);
END COMPONENT;
signal cp : std_logic := '0';
signal sel : std_logic_vector(1 downto 0) := "00";
signal outcp : std_logic;
constant cp_period : time := 10 ns;
BEGIN
uut: Freq4Sel PORT MAP (
cp => cp,
sel => sel,
outcp => outcp
);
cp_process :process
begin
cp <= '0';
wait for cp_period/2;
cp <= '1';
wait for cp_period/2;
end process;
stim_proc: process
begin
wait for 100 ns;
sel <= "10";
wait for cp_period*10;
wait;
end process;
END;