有没有一种方法可以使用数据路径和控制单元在Verilog中为一个用户编写猪游戏？

Question

This is the ASM i have used for the code 我正在尝试编写一个使用Verilog实现猪游戏的程序。我必须为此程序设置一个数据路径和控制单元，但我确实使用常规的ASM图表进行了尝试，但是在数据路径和控制单元中实现它有问题

到目前为止，这是我常规的操作方式

module piggame( clock , counter , reset , push , sum , yes , no , tsum , dice1  );
input clock , reset , push , yes , no ; // push is a button on the board that implements rolling of a dice in high speed
output reg [7:1] sum= 0  , tsum = 0 ;  // sum is the total sum and tsum is the sum of the turn 
output reg [3:0] counter = 0 ; // counter to count for 5 turns 
 reg [3:0] present ;// present state register
 wire [3:0] d1 ; // dice value recorded from the call to the fucntion changeclock 
output reg [3:0] dice1 = 0  ;

parameter s0 = 4'd0 , s1 = 4'd1  , s2 = 4'd2 ;

changeclock uut (.clock(clock),.reset(reset),.Dice1(d1)); // this calls for a dice value were a 100mhz clock is given as an input so that 
// the user can have a random dice value . 


 reg [3:0]next ;

always@ (*) 
begin

case(present) 
s0 : if ( counter > 6 ) next = s0 ;
else if ( counter < 6 && push == 1 ) next = s1 ;
s1 : if ( push == 0 && d1 ==1 ) next = s0 ; 
    else if (push ==0 && d1 != 0 ) next = s2 ;
s2 : if ( yes ) next = s0 ;
        else if ( no ) next = s0 ;
        default :next = s0 ;
endcase
end

always@( posedge clock , posedge reset) 
if ( reset) present <= s0 ;
else present <= next ;


always @( posedge clock) 

case ( present ) 
s1 : if ( push == 0 )begin 

         if ( d1 ==1)
            begin 
            dice1 <= d1 ;

            sum <= sum ; counter <= counter+ 1 ;
            tsum <= 0 ;
             end  

        else if ( d1 != 1 ) 
        begin 
         tsum <= tsum + d1;end
        end 

 s2 :if ( yes )
  counter = counter ;
  else if ( no) begin 
  sum <= sum + tsum ;
  tsum <= 0 ;
  counter <= counter + 1 ;  end 


endcase

endmodule

我能够在仿真时生成波形，但是在xilinx板上运行时，我无法显示骰子值。当我按下用作高速时钟的按钮以生成随机骰子值时，该值不会改变。

以下是我用来生成波形的测试台的代码

module simulation();
reg clock , reset , push ,yes,  no ;
wire [3:0] counter ;
wire [7:0] sum , tsum ;

wire [3:0] present , next ; 
wire [3:0] dice1 ;
crapgame uuts( clock , counter , reset , push , sum , yes , no , tsum , 
dice1);



initial
clock=0;
always 
#5 clock=~clock;
    initial begin
    reset = 1'b1;#100;
    reset = 1'b0;#8000;                  
    end

    initial begin
        push = 1'b1;#100;
    push = 1'b0;#100;
    push = 1'b1;#100;
    push = 1'b0;#100;
    push = 1'b1;#100;
    push = 1'b0;#100;
    push = 1'b0;#100; end

    initial begin
    yes = 1'b0;#100;
    yes = 1'b0;#100;
    yes = 1'b0;#100;
    yes = 1'b0;#100;

    end
    initial begin 
    no = 1'b1;#100;
    no = 1'b1;#100;
    no = 1'b1;#100;
    no = 1'b1;#100;
    no = 1'b1;#100;
    no = 1'b1;#100;
    no = 1'b1;#100;

    end
    endmodule