Question

因此，我应该通过使用组件来实现一个简单的最小成本函数F。我已经按照我的老师的注释写了我认为是正确的方法，但是出现了错误（12004）：端口“ out1”在实例“ U3”的原始“ AND2”中不存在，我认为有些东西与我的组件的声明，但我找不到什么问题。我两天前才开始使用VHDL，所以我至少可以说是新手； p由于我在互联网上找不到其他任何东西，因此非常感谢您的帮助。我拥有比我更多的变量的原因是我打算解决此错误后，添加更多代码。：）

library ieee, my_func;
USE ieee.std_logic_1164.all, my_func.basic_func.all;
ENTITY Ergasia IS
        PORT (X1,X2,X3,X4,X5:IN std_logic;
        F,G:out std_logic);
END Ergasia;
architecture structural of Ergasia is

        component AND2 
                port(in1, in2: in std_logic;
                        out1: out std_logic);
        end component;
        component AND3
                port(in1, in2, in3: in std_logic;
                        out1: out std_logic);
        end component;
        component OR3
                port(in1, in2, in3: in std_logic;
                        out1: out std_logic);
        end component;
        component NOT1
                port(in1: in std_logic;
                        out1: out std_logic);
        end component;
        signal X1_NOT, X2_NOT, X3_NOT, X4_NOT, X5_NOT, B1, B2, B3:std_logic;
begin
        U0: NOT1 port map (X1,X1_NOT);
        U1: NOT1 port map (X2,X2_NOT);
        U2: NOT1 port map (X3,X3_NOT);
        U3: AND2 port map (X1_NOT,X2_NOT,B1);
        U4: AND2 port map (X2, X3_NOT, B2);
        U5: AND3 port map (X1, X2, X5, B3);
        U6: OR3 port map (B1, B2, B3,G);
end structural;

我的basic_func也是这样：

library ieee;
use ieee.std_logic_1164.all;

package basic_func is

    component AND2
            port(in1,in2:in std_logic; out1:out std_logic);
    end component;

    component OR3
            port(in1,in2,in3:in std_logic; out1:out std_logic);
    end component;

    component AND3
            port(in1,in2,in3:in std_logic; out1:out std_logic);
    end component;
end package basic_func;



library ieee;
use ieee.std_logic_1164.all;
    entity AND2 is
        port(in1,in2:in std_logic; out1:out std_logic);
    end AND2;
    architecture model_and2 of AND2 is
        begin
            out1 <= in1 and in2;
    end model_and2;

library ieee;
use ieee.std_logic_1164.all;
    entity AND3 is
        port(in1,in2,in3:in std_logic;out1:out std_logic);
    end AND3;
    architecture model_and3 of AND3 is
        begin
            out1 <= (in1 and in2) and in3;
    end model_and3;

library ieee;
use ieee.std_logic_1164.all;    
        entity OR3 is
        port(in1,in2,in3:in std_logic;out1:out std_logic);
    end OR3;
    architecture model_or3 of OR3 is
        begin
            out1 <= (in1 and in2) and in3;
    end model_or3;

即使我正确声明了所有内容，为什么VHDL给我一个12004错误？

0 个答案: