合并掩护点以创建汇总

时间:2019-03-08 18:46:37

标签: code-coverage system-verilog uvm cadence

`define A 'd1
`define B 'd2
`define C 'd3
`define D 'd4
`define E 'd5
`define F 'd6
`define I 'd7
`define J 'd8

module testModule(input clk,
                        input CReset,
                        input[4;0] Opcode_P0I1,
                        input[4;0] Opcode_P0I2,
                        input[4;0] Opcode_P0I3,
                        input[4;0] Opcode_P0I4,
                        input[4;0] Opcode_P1I1,
                        input[4;0] Opcode_P1I2,
                        input[4;0] Opcode_P1I3,
                        input[4;0] Opcode_P1I4,
                        input P0V,
                        input P1V,
                        input P0IsFe,
                        input P1IsFe,
                        input P0I1PAllow,
                        input P0I2PAllow,
                        input P0I3PAllow,
                        input P0I4PAllow,
                        input P1I1PAllow,
                        input P1I2PAllow,
                        input P1I3PAllow,
                        input P1I4PAllow,
                        input I1VT0,
                        input I1VT1,
                        input I1VT2,
                        input I1VT4,
                        input I2VT0,
                        input I2VT1,
                        input I2VT2,
                        input I2VT3,
                        input I3VT0,
                        input I3VT1,
                        input I3VT2,
                        input I3VT3,
                        input I4VT0,
                        input I4VT1,
                        input I4VT2,
                        input I4VT3,
                        input[3:0] P0TId,
                        input[3:0] P1TId);
covergroup cg_Abc @(posedge clk);
    option.per_instance = 1;
    cp_P0I1_IsSquare: coverpoint Opcode_P0I1 iff (P0V == 1 && P0IsFe == 1 && P0I1PAllow == 1 && (I1VT0 && P0TId == 2**0  || I1VT1 && P0TdId == 2**1 || I1VT2 && P0TId == 2**2 || I1VT3 &&  P0TId == 2**3)) {option.weight = 0;type_option.weight = 0; bins derp = {`A,`B,`C};}
    cp_P0I2_IsSquare: coverpoint Opcode_P0I2 iff (P0V == 1 && P0IsFe == 1 && P0I2PAllow == 1 && (I2VT0 && P0TId == 2**0  || I2VT1 && P0TdId == 2**1 || I2VT2 && P0TId == 2**2 || I2VT3 &&  P0TId == 2**3)) {option.weight = 0;type_option.weight = 0; bins derp = {`A,`B,`C};}
    cp_P0I3_IsSquare: coverpoint Opcode_P0I3 iff (P0V == 1 && P0IsFe == 1 && P0I3PAllow == 1 && (I3VT0 && P0TId == 2**0  || I3VT1 && P0TdId == 2**1 || I3VT2 && P0TId == 2**2 || I3VT3 &&  P0TId == 2**3)) {option.weight = 0;type_option.weight = 0; bins derp = {`A,`B,`C};}
    cp_P0I4_IsSquare: coverpoint Opcode_P0I4 iff (P0V == 1 && P0IsFe == 1 && P0I4PAllow == 1 && (I4VT0 && P0TId == 2**0  || I4VT1 && P0TdId == 2**1 || I4VT2 && P0TId == 2**2 || I4VT3 &&  P0TId == 2**3)) {option.weight = 0;type_option.weight = 0; bins derp = {`A,`B,`C};}
    cp_P1I1_IsSquare: coverpoint Opcode_P1I1 iff (P1V == 1 && P1IsFe == 1 && P1I1PAllow == 1 && (I1VT0 && P1TId == 2**0  || I1VT1 && P1TdId == 2**1 || I1VT2 && P1TId == 2**2 || I1VT3 &&  P1TId == 2**3)) {option.weight = 0;type_option.weight = 0; bins derp = {`A,`B,`C};}
    cp_P1I2_IsSquare: coverpoint Opcode_P1I2 iff (P1V == 1 && P1IsFe == 1 && P1I2PAllow == 1 && (I2VT0 && P1TId == 2**0  || I2VT1 && P1TdId == 2**1 || I2VT2 && P1TId == 2**2 || I2VT3 &&  P1TId == 2**3)) {option.weight = 0;type_option.weight = 0; bins derp = {`A,`B,`C};}
    cp_P1I3_IsSquare: coverpoint Opcode_P1I3 iff (P1V == 1 && P1IsFe == 1 && P1I3PAllow == 1 && (I3VT0 && P1TId == 2**0  || I3VT1 && P1TdId == 2**1 || I3VT2 && P1TId == 2**2 || I3VT3 &&  P1TId == 2**3)) {option.weight = 0;type_option.weight = 0; bins derp = {`A,`B,`C};}
    cp_P1I4_IsSquare: coverpoint Opcode_P1I4 iff (P1V == 1 && P1IsFe == 1 && P1I4PAllow == 1 && (I4VT0 && P1TId == 2**0  || I4VT1 && P1TdId == 2**1 || I4VT2 && P1TId == 2**2 || I4VT3 &&  P1TId == 2**3)) {option.weight = 0;type_option.weight = 0; bins derp = {`A,`B,`C};}

    cp_P0I1_IsCircle: coverpoint Opcode_P0I1 iff (P0V == 1 && P0I1PAllow == 0 && (I1VT0 && P0TId == 2**0  || I1VT1 && P0TdId == 2**1 || I1VT2_DE2 && P0TId == 2**2 || I1VT3 &&  P0TId == 2**3)) {option.weight = 0;type_option.weight = 0; bins bxx = {`D,`E,`F,`G,`H,`I,`J};}
    cp_P0I2_IsCircle: coverpoint Opcode_P0I2 iff (P0V == 1 && P0I2PAllow == 0 && (I2VT0 && P0TId == 2**0  || I2VT1 && P0TdId == 2**1 || I2VT2_DE2 && P0TId == 2**2 || I2VT3 &&  P0TId == 2**3)) {option.weight = 0;type_option.weight = 0; bins bxx = {`D,`E,`F,`G,`H,`I,`J};}
    cp_P0I3_IsCircle: coverpoint Opcode_P0I3 iff (P0V == 1 && P0I3PAllow == 0 && (I3VT0 && P0TId == 2**0  || I3VT1 && P0TdId == 2**1 || I3VT2_DE2 && P0TId == 2**2 || I3VT3 &&  P0TId == 2**3)) {option.weight = 0;type_option.weight = 0; bins bxx = {`D,`E,`F,`G,`H,`I,`J};}
    cp_P0I4_IsCircle: coverpoint Opcode_P0I4 iff (P0V == 1 && P0I4PAllow == 0 && (I4VT0 && P0TId == 2**0  || I4VT1 && P0TdId == 2**1 || I4VT2_DE2 && P0TId == 2**2 || I4VT3 &&  P0TId == 2**3)) {option.weight = 0;type_option.weight = 0; bins bxx = {`D,`E,`F,`G,`H,`I,`J};}
    cp_P1I1_IsCircle: coverpoint Opcode_P1I1 iff (P1V == 1 && P1I1PAllow == 0 && (I1VT0 && P1TId == 2**0  || I1VT1 && P1TdId == 2**1 || I1VT2 && P1TId == 2**2 || I1VT3 &&  P1TId == 2**3)) {option.weight = 0;type_option.weight = 0; bins bxx = {`D,`E,`F,`G,`H,`I,`J};}
    cp_P1I2_IsCircle: coverpoint Opcode_P1I2 iff (P1V == 1 && P1I2PAllow == 0 && (I2VT0 && P1TId == 2**0  || I2VT1 && P1TdId == 2**1 || I2VT2 && P1TId == 2**2 || I2VT3 &&  P1TId == 2**3)) {option.weight = 0;type_option.weight = 0; bins bxx = {`D,`E,`F,`G,`H,`I,`J};}
    cp_P1I3_IsCircle: coverpoint Opcode_P1I3 iff (P1V == 1 && P1I3PAllow == 0 && (I3VT0 && P1TId == 2**0  || I3VT1 && P1TdId == 2**1 || I3VT2 && P1TId == 2**2 || I3VT3 &&  P1TId == 2**3)) {option.weight = 0;type_option.weight = 0; bins bxx = {`D,`E,`F,`G,`H,`I,`J};}
    cp_P1I4_IsCircle: coverpoint Opcode_P1I4 iff (P1V == 1 && P1I4PAllow == 0 && (I4VT0 && P1TId == 2**0  || I4VT1 && P1TdId == 2**1 || I4VT2 && P1TId == 2**2 || I4VT3 &&  P1TId == 2**3)) {option.weight = 0;type_option.weight = 0; bins bxx = {`D,`E,`F,`G,`H,`I,`J};}

    cr_P0I1I2_IsSqauarexIsCircle : cross cp_P0I1_IsSquare,cp_P0I2_IsCircle{option.weight = 0;type_option.weight = 0;}
    cr_P0I2I3_IsSqauarexIsCircle : cross cp_P0I2_IsSquare,cp_P0I3_IsCircle{option.weight = 0;type_option.weight = 0;}
    cr_P0I3I4_IsSqauarexIsCircle : cross cp_P0I3_IsSquare,cp_P0I4_IsCircle{option.weight = 0;type_option.weight = 0;}
    AggregateCov1 : ?

    cr_P1I1I2_IsSqauarexIsCircle : cross cp_P1I1_IsSquare,cp_P1I2_IsCircle{option.weight = 0;type_option.weight = 0;}
    cr_P1I2I3_IsSqauarexIsCircle : cross cp_P1I2_IsSquare,cp_P1I3_IsCircle{option.weight = 0;type_option.weight = 0;}
    cr_P1I3I4_IsSqauarexIsCircle : cross cp_P1I3_IsSquare,cp_P1I14_IsCircle{option.weight = 0;type_option.weight = 0;}
    AggregateCov2 : ?
  endgroup
  cg_Abc cg_Abc_inst = new();
endmodule

我正在寻找AggregateCov1,它告诉cr_P0I1I2_IsSqauarexIsCircle,cr_P0I2I3_IsSqauarexIsCircle,cr_P0I3I4_IsSqauarexIsCircle中的任何一个是否命中。本质上讲,在[Opcode_P0I1,Opcode_P0I2,Opcode_P0I3,Opcode_P0I4]组中,我至少有一个彼此相邻的正方形和一个圆形。

还要寻找AggregateCov2,它告诉我在组[Opcode_P0I1,Opcode_P0I2,Opcode_P0I3,Opcode_P0I4]或[Opcode_P1I1,Opcode_P1I2,Opcode_P1]中是否至少有一个正方形和一个彼此相邻的圆

2 个答案:

答案 0 :(得分:0)

无需执行此操作,因为您需要击中所有掩护点a,b,c AND 才能获得该掩护组的100%覆盖率。

但是,如果您坚持要使用覆盖点表达式

AggregateCoverpoint: coverpoint v_a | v_b | v_c;

答案 1 :(得分:0)

使用assign语句创建新线路,可以解决此问题。