是否也可以通过具有+ uvm_set_type_override = test1,test2来覆盖通过+ UVM_TESTNAME = test1指定的uvm测试?

时间:2019-02-11 16:43:32

标签: system-verilog uvm

我想知道是否可以通过+ uvm_set_type_override覆盖通过+ UVM_TESTNAME在命令行中指定的测试。

I have tried it and this is what i see in prints in log. 
UVM_INFO @ 0: reporter [RNTST] Running test Test1...
UVM_INFO @ 0: reporter [UVM_CMDLINE_PROC] Applying type override from the command line: +uvm_set_type_override=Test1,Test2

在我看来,首先创建测试组件,然后应用工厂替代?

我在uvm_root.svh中看到以下代码段

 // if test now defined, create it using common factory
 if (test_name != "") begin
   if(m_children.exists("uvm_test_top")) begin
     uvm_report_fatal("TTINST",
         "An uvm_test_top already exists via a previous call to run_test", UVM_NONE);
     #0; // forces shutdown because $finish is forked
  end
   $cast(uvm_test_top, factory.create_component_by_name(test_name,
         "", "uvm_test_top", null));

它正在使用工厂,但是我不知道是否使用了强制覆盖。下面我还会看到代码。

 begin
  if(test_name=="") 
     uvm_report_info("RNTST", "Running test ...", UVM_LOW); 
  else if (test_name == uvm_test_top.get_type_name())
     uvm_report_info("RNTST", {"Running test ",test_name,"..."}, UVM_LOW); 
  else
     uvm_report_info("RNTST", {"Running test ",uvm_test_top.get_type_name()," (via factory override for test \"",test_name,"\")..."}, UVM_LOW);
 end

我想知道上面的“ else”部分是否曾经执行过?或在什么条件下执行?

1 个答案:

答案 0 :(得分:0)

UVM中的命令行处理顺序似乎存在问题-UVM_TESTNAME在所有其他选项之前被单独处理。

可以在初始块中调用run_test()之前设置覆盖。

但是设置测试名称,然后在同一命令行中覆盖它有什么意义呢?为什么不使用覆盖的测试名称作为测试?