FPGA板Verilog上的贪睡按钮仿真

Question

我正在为Verilog的FPGA板编写程序，但有两个我似乎无法弄清的问题。对于我每次按下一个按钮，我希望一个指示灯点亮，然后两个，然后三个，依此类推。我希望它实质上显示按钮按下的按钮数量。然后我的另一个问题是我的显示屏上有一个向上计数的秒计时器，该计时器在按下一个按钮时启动，而在按下另一个按钮时停止。我想更改程序，使停止按钮将计时器重置为00:00，并自动计数直到再次按下按钮为止。任何一个问题的帮助将不胜感激。

用于在按钮按下时显示LED的LED显示模块：

module LED_Counter (clk, start, snooze, reset, snooze0, snooze1, snooze2, snooze3, snooze4, snooze5, snooze6,  snooze7, snooze8, snooze9);

    input start, snooze, reset, clk;
    output reg snooze0, snooze1, snooze2, snooze3, snooze4, snooze5, snooze6, snooze7, snooze8, snooze9;

    parameter zero = 4'b0000, one = 4'b0001, two = 4'b0010, three = 4'b0011, four = 4'b0100, five = 4'b0101, six = 4'b0110, seven = 4'b0111,  eight = 4'b1000, nine = 4'b1001, ten = 4'b1010;
    reg [3:0] state, next_state;

 always @(*) begin
    if (reset) state = zero;
    else if (snooze) state = next_state;
    end




    //next state combinational circuit (next state logic)
    always @(state) begin
        case (state)

            zero: next_state =one;
            one: next_state =two;
            two: next_state = three;
            three: next_state =four;
            four: next_state =five;
            five: next_state =six;
            six: next_state = seven;
            seven: next_state = eight;
            eight: next_state = nine;
            nine: next_state = ten;


            default: next_state = zero;
        endcase
    end

    //output combinational circuit (output logic)
    always @(state) begin
        case (state)
            zero:{snooze0, snooze1, snooze2, snooze3, snooze4, snooze5, snooze6, snooze7, snooze8, snooze9} = 10'b0000000000;
            one:{snooze0, snooze1, snooze2, snooze3, snooze4, snooze5, snooze6, snooze7, snooze8, snooze9} = 10'b1000000000;
            two:{snooze0, snooze1, snooze2, snooze3, snooze4, snooze5, snooze6, snooze7, snooze8, snooze9} = 10'b1100000000;
            three:{snooze0, snooze1, snooze2, snooze3, snooze4, snooze5, snooze6, snooze7, snooze8, snooze9} = 10'b1110000000;
            four:{snooze0, snooze1, snooze2, snooze3, snooze4, snooze5, snooze6, snooze7, snooze8, snooze9} = 10'b1111000000;
            five: {snooze0, snooze1, snooze2, snooze3, snooze4, snooze5, snooze6, snooze7, snooze8, snooze9} = 10'b1111100000;
            six: {snooze0, snooze1, snooze2, snooze3, snooze4, snooze5, snooze6, snooze7, snooze8, snooze9} = 10'b1111110000;
            seven: {snooze0, snooze1, snooze2, snooze3, snooze4, snooze5, snooze6, snooze7, snooze8, snooze9} = 10'b1111111000;
            eight: {snooze0, snooze1, snooze2, snooze3, snooze4, snooze5, snooze6, snooze7, snooze8, snooze9} = 10'b1111111100;
            nine: {snooze0, snooze1, snooze2, snooze3, snooze4, snooze5, snooze6, snooze7, snooze8, snooze9} = 10'b1111111110;
            ten: {snooze0, snooze1, snooze2, snooze3, snooze4, snooze5, snooze6, snooze7, snooze8, snooze9} = 10'b1111111111;


            default: {snooze0, snooze1, snooze2, snooze3, snooze4, snooze5, snooze6, snooze7, snooze8, snooze9} = 10'b0000000000;
        endcase

    end
endmodule

顶级模块（我还有其他用于定时器输出的模块）

module Final_Project (KEY, MAX10_CLK1_50, HEX0, HEX1, HEX2, HEX3, SW, LEDR);
    input [1:0] KEY, SW;

    input MAX10_CLK1_50;
    output [6:0] HEX0, HEX1, HEX2, HEX3;
    output [9:0] LEDR;


    wire [9:0] LEDR;
    wire clock_100hz, clk;
    wire reset;
    wire [15:0]T;
    wire [27:0]h;
    wire start, stop, enable, snooze;
    wire snooze0, snooze1, snooze2, snooze3, snooze4, snooze5, snooze6, snooze7, snooze8, snooze9;

    assign HEX0 = ~h[6:0];
    assign HEX1 = ~h[13:7];
    assign HEX2 = ~h[20:14];
    assign HEX3 = ~h[27:21];

    assign LEDR[0] = snooze0, LEDR[1] = snooze1 ,LEDR[2] = snooze2, LEDR[3] = snooze3 ,LEDR[4] = snooze4 ,LEDR[5] = snooze5, LEDR[6] = snooze6, LEDR[7] = snooze7, LEDR[8] = snooze8, LEDR[9] = snooze9;


    assign reset = SW[0];
    assign start = ~KEY[0];
    assign snooze = ~KEY[1];

    ClockDivider inst0 (MAX10_CLK1_50, clock_100hz);
    StateMachine inst99 (clock_100hz, start, snooze, reset, enable);
    sixteen_bit_counter inst10 (clock_100hz, enable, reset, T[15:0]);
    bcd_to_sevenseg inst2 (T[3:0], h[6:0]);
    bcd_to_sevenseg inst3 (T[7:4], h[13:7]);
    bcd_to_sevenseg inst4 (T[11:8], h[20:14]);
    bcd_to_sevenseg inst5 (T[15:12], h[27:21]);
    LED_Counter inst6 (clock_100hz, start, snooze, reset, snooze0, snooze1, snooze2, snooze3, snooze4, snooze5, snooze6,  snooze7, snooze8, snooze9);



endmodule