Question

我正在尝试在VHDL-2008中实现通用解串器。（具体地说，我的目标是让Vivado在VHDL-2008模式下可以合成的东西。）

我在下面包括了我当前的代码。实体端口声明为反序列化的输出字指定了不受限制的std_logic_vector DATA_OUT。

问题在于，在此实现中，如果我希望能够处理32位字，则需要指定一个CounterType如下：

type CounterType is range 0 to 31;

我还没有办法以有效的VHDL方式从DATA_OUT端口的大小中写出一种CounterType定义的方法，更不用说Vivado的编译器可以接受的方式了。

有没有办法做到这一点？（即，定义范围类型，该范围对应于不受约束的实际参数的范围吗？）

如果没有，我有什么选择来保持此反序列化器实现尽可能通用，即能够针对不同的输出字长实例化它？

（注意：我宁愿不向实体接口添加泛型的方法，因为这与实例化时指定DATA_OUT的范围似乎是多余的。但是如果不能这样做，我会对这些解决方案也很感兴趣。）

library ieee;
use ieee.std_logic_1164.all;

entity deserializer is

    -- The deserializer accepts its single input bit DATA_IN whenever (DATA_IN_VALID and DATA_IN_READY) = '1'.
    -- The deserializer drops its output word DATA_OUT and proceeds whenever (DATA_OUT_VALID and DATA_OUT_READY) = '1'.

    port (
        CLK            : in  std_logic;
        RESET          : in  std_logic;
        DATA_IN        : in  std_logic;
        DATA_IN_VALID  : in  std_logic;
        DATA_IN_READY  : out std_logic;
        DATA_OUT       : out std_logic_vector;
        DATA_OUT_VALID : out std_logic;
        DATA_OUT_READY : in  std_logic
    );

end entity deserializer;


architecture arch of deserializer is

-- This implementation is designed to have no wait states: if a continuous stream of input bits is offered,
-- and the deserializer can offload its output words unimpeded, DATA_IN_READY will always be true, i.e.,
-- we'll never throttle our input; we'll process 1 bit per clock cycle.

type CounterType is range 0 to 31; -- should correspond to the index range of DATA_OUT.

type StateType is record
    -- Internal state.
    counter     : CounterType;
    data_in_bit : std_logic; -- Used to store an input bit while waiting to offload the output word in state (counter == 0).
    -- Output registers.
    data_in_ready  : std_logic;
    data_out       : std_logic_vector(DATA_OUT'range);
    data_out_valid : std_logic;
end record StateType;

constant reset_state : StateType := (
    counter        => 0,
    data_in_bit    => '-',
    data_in_ready  => '1',
    data_out       => (others => '-'),
    data_out_valid => '0'
  );

signal current_state : StateType := reset_state;
signal next_state    : StateType;

begin

    combinatorial: process (all) is
    variable state: StateType;
    begin
        -- Calculate next state based on current state and inputs.
        if RESET = '1' then
            -- Handle synchronous reset.
            state := reset_state;
        else
            -- Start from current state.
            state := current_state;

            if state.counter = 0 then
                -- Note: we may have a pending output, waiting to be accepted.
                if state.data_out_valid = '1' and DATA_OUT_READY = '1' then
                    state.data_out := (others => '-');
                    state.data_out_valid := '0';
                end if;

                if state.data_in_ready = '1' and DATA_IN_VALID = '1' then
                    state.data_in_bit := DATA_IN;
                    state.data_in_ready := '0';
                end if;

                if state.data_out_valid = '0' and state.data_in_ready = '0' then
                    state.data_out(state.data_out'right) := state.data_in_bit;
                    state.data_in_bit := '-';
                    state.counter := state.counter + 1;
                    state.data_in_ready := '1';
                end if;
            else
                if state.data_in_ready = '1'and DATA_IN_VALID = '1' then
                    state.data_out := state.data_out sll 1;
                    state.data_out(state.data_out'right) := DATA_IN;
                    if state.counter = CounterType'high then
                        state.data_out_valid := '1';
                        state.counter := 0;
                    else
                        state.counter := state.counter + 1;
                    end if;
                end if; 
            end if;

        end if;

        -- Schedule next state for update at next rising clock edge.
        next_state <= state;

        -- Drive entity outputs from current state.
        DATA_IN_READY  <= current_state.data_in_ready;
        DATA_OUT       <= current_state.data_out;
        DATA_OUT_VALID <= current_state.data_out_valid;

    end process combinatorial;

    sequential: process (CLK) is
    begin
        if rising_edge(CLK) then
            current_state <= next_state;
        end if;
    end process sequential;

end architecture arch;

Answer 1

CounterType的大小可以为DATA_OUT'low to DATA_OUT'high。您应该声明一个子类型，而不是声明一个与称为“ nteger”的预定义整数类型不兼容的全新整数类型，

subtype CounterType is integer range DATA_OUT'low to DATA_OUT'high;

如果这些工具完全符合VHDL-2008标准，则它也应接受以下条件：

subtype CounterType is integer range DATA_OUT'range;

有没有一种方法可以根据实体端口中声明的无约束向量的范围来定义范围类型？

1 个答案: