Question

我需要在vhdl中生成一个0到1023之间的随机整数，但是我在互联网上找不到很好的资源。请问有人帮我吗？

Answer 1

下面是生成具有均匀（偶数）分布的[0：1023]范围内的整数的示例。

请注意，floor运算必须在与最大值+ 1相乘后使用，在这种情况下，必须为1023 + 1 = 1024，以确保[0： 1023]，因为如注释中的示例“在VHDL测试平台中生成随机数”那样使用不带底数的整数（因此integer(x * 1023)）将导致四舍五入到最接近的值（从一半向上舍入），因此仅给出范围中的第一个和最后一个值（0和1023）。

entity tb is
end entity;

library ieee;
use ieee.math_real.uniform;
use ieee.math_real.floor;

architecture sim of tb is
begin
  process is
    variable seed1 : positive;
    variable seed2 : positive;
    variable x : real;
    variable y : integer;
  begin
    seed1 := 1;
    seed2 := 1;
    for n in 1 to 10 loop
      uniform(seed1, seed2, x);
      y := integer(floor(x * 1024.0));
      report "Random number in 0 .. 1023: " & integer'image(y);
    end loop;
    wait;
  end process;
end architecture;

Answer 2

在评论中，我写了“寻找LFSR随机数生成器”，但是使用那些可能并不会立即显而易见的陷阱有一些陷阱。

它们不能生成零值。
他们不能两次产生相同的数字。
每个数字在2 ^ n个周期中仅出现一次。
数字高度“相关”两倍。

我编写并测试了一个16位生成器，试图解决上述一些问题。但是请注意，结果将始终是伪随机数，因此不要期望真正的随机性。

我之所以使用Verilog，是因为它的编写速度是VHDL的五倍，但是对于VHDL程序员而言，翻译应该是微不足道的。

//
// 16-bit Pseudo random number generator
// Using Linear Feedback Shift Register
//
// No copyright : Freeware, 18 Nov. 2018 
//
//

// The LFSR polynomial is taken from a (by now almost famous)
// application note from Xilinx.
// Those polynomials are selected for using minimal logic
// not for getting good 'randomness'.
// Using an LFSR alone is not good:
// - They can not generate the value zero.
// - They can not produce the same number twice.
// - Every number appears only once in 2^n cycles.
// - The numbers are highly 'related' by a factor two.
//  e.g. an 8-bit LFSR would take steps:
//  1, 2, 4, 8, 16, 32, 64, 128, 33, 66, 132, 41, 82 
//  
//  Therefore I use only 16 of 32 bits and re-order
//  the selected bits. Even then it may take a while before,
//  (what our feelings say!) a more random sequence of number
//  appears. 
//  
// 
// Other LFSRs polynomials (From Xilinx app. note) 
//  32 =  32,31,30,10,0 (used here)
//  40 =  40,21,19,2,0
//  48 =  48,28,27,1,0
//  56 =  56,22,21,1,0
//  64 =  64, 4, 3,1,0
//  72 =  72,53,47,6,0
//  80 =  80,38,35,3,0
//  88 =  88,72,71,1,0
//  96 =  96,49,47,2,0
// 112 = 112,45,43,2,0
// 128 = 128,29,27,2,0
// 
// 
// Know deficiencies:
// -  Using a seed of zero will only produce zeros. 
//    This module does not check that!
// -  Always running. Might add a 'next' number 
//    input for power savings.
// 

module prng16
// Do NOT change these parameters unless you know what you are doing
#(parameter poly    = 32'hC0000400, // max length 32, bit LFSR bits 31,30,10 are set
            degree  = 32
 )
( 
  input   reset_n,
  input   clk,
  input   set,
  input   [degree-1:0] seed,
  output  [15:0] rnd
);

reg [degree-1:0] lfsr,feedback;

   always @(posedge clk or negedge reset_n)
   begin
      if (!reset_n)
         // Futile attempt to start somewhat random.
         // I know: this value is too big for some values of 
         // degree, but better then too small.
         lfsr <= { {(degree/3){3'b101}},2'b10};
      else
         if (set)
            lfsr <= seed;
         else
            lfsr <= feedback;
   end

integer n;

   always @( * )
   begin
      feedback[0]= lfsr[degree-1];
      for (n=1; n<degree; n=n+1)         
        feedback[n] = poly[n]==1'b0 ? lfsr[n-1] : lfsr[n-1]^lfsr[degree-1];
   end

   // Pick 16 bits (indices randomly chosen)
   assign rnd = { lfsr[27], lfsr[16], lfsr[ 6], lfsr[22], 
                  lfsr[20], lfsr[ 0], lfsr[18], lfsr[26],
                  lfsr[10], lfsr[ 9], lfsr[25], lfsr[19], 
                  lfsr[11], lfsr[ 7], lfsr[28], lfsr[ 8]};

endmodule

在VHDL中生成随机整数

2 个答案: