为少量输入获取正确的值。不适用于4 * 4乘法器中的所有组合

Question

我正在编写4 * 4乘数的代码。虽然，我得到的输入值很少，但其他输入值却给我错误。请建议我这里存在哪些逻辑错误，因为我无法发现它们

---

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

    entity multiplier is
        Port ( a : in  std_logic_vector (3 downto 0);
               b : in std_logic_vector (3 downto 0);
               result : out std_logic_vector (7 downto 0));
    end multiplier;

    architecture Behavioral of multiplier is

    signal P0: std_logic_vector(7 downto 0);
    signal P1: std_logic_vector(7 downto 0);
    signal SP1: std_logic_vector(7 downto 0);
    signal P2: std_logic_vector(7 downto 0);
    signal SP2: std_logic_vector(7 downto 0);
    signal P3: std_logic_vector(7 downto 0);

    component genericadder

            Port ( a : in std_logic_vector(3 downto 0);
                   b : in std_logic_vector(3 downto 0);
                   sum : out std_logic_vector (4 downto 0));
            end component;  

    begin 

    result(0) <= a(0) and b(0);
    P0(0) <= a(0) and b(1);
    P0(1) <= a(0) and b(2);
    P0(2) <= a(0) and b(3);
    P0(3) <='0';

    P0(4) <= a(1) and b(0);
    P0(5) <= a(1) and b(1);
    P0(6) <= a(1) and b(2);
    P0(7) <= a(1) and b(3);

    ga_for : genericadder
    port map(
     a =>P0( 3 downto 0),
     b =>P0( 7 downto 4),   
     sum =>P1(4 downto 0));    


    result(1)<= P1(0);
    SP1<= std_logic_vector(shift_right(unsigned(P1),1));
    P1(4) <= a(2) and b(0);
    P1(5) <= a(2) and b(1);
    P1(6) <= a(2) and b(2);
    P1(7) <= a(2) and b(3);

    ga_for1 : genericadder
    port map(
     a =>SP1( 3 downto 0),
     b =>P1( 7 downto 4),
     sum =>P2(4 downto 0));

    result(2) <= P2(0);
    SP2<= std_logic_vector(shift_right(unsigned(P2),1));
    P2(4) <= a(3) and b(0);
    P2(5) <= a(3) and b(1);
    P2(6) <= a(3) and b(2);
    P2(7) <= a(3) and b(3);

    ga_for2 : genericadder
    port map(
     a =>SP2( 3 downto 0),
     b =>P2( 7 downto 4),
     sum =>P3(4 downto 0));

    result(3)<=P3(0);


    result(4)<=P3(1);
    result(5)<=P3(2);
    result(6)<=P3(3);
    result(7)<=P3(4);


    end Behavioral;

---

---

entity genericadder is
 generic (
    n : Integer:=4       
     );
    Port ( a : in STD_LOGIC_VECTOR (n-1 downto 0);
           b : in STD_LOGIC_VECTOR (n-1 downto 0);
           sum : out STD_LOGIC_VECTOR (n downto 0));
end genericadder;

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genericadder由完全加法器组成。请让我知道错误。我真的无法前进