这段代码怎么说?我如何解释其电路?
module add(input logic clock, output logic[7:0] f);
logic[7:0] a, b, c;
always_ff @(posedge clock)
begin
a <= b + c;
b = c + a;
c = a + b;
end
assign f = c;
endmodule
答案 0 :(得分:0)
您应将此代码解释为
module add(input logic clock, output logic[7:0] f);
logic[7:0] a, b;
always_ff @(posedge clock)
a <= b + f;
always_ff @(posedge clock)
b <= f + a;
always_ff @(posedge clock)
f <= a + b;
endmodule
从逻辑上讲,这与您编写的内容等效,但是对于在f
上对输出posedge clock
进行采样的任何代码,都可以提供可预测的仿真结果