兄弟在序言

Question

我当前面临的一个问题是我需要找到谁是他的兄弟，例如brother（X，awang）。但是，当我在序言中运行程序时，它给了我错误的陈述。这是我的代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity SERDES_Testbench is
--  Port ( );
end SERDES_Testbench;

architecture Behavioral of SERDES_Testbench is
constant Dbits : integer := 16;

component SerDes is
    generic ( 
        Dbits : integer := 16
           );   
    Port (
           serial_clk : in STD_LOGIC;
           clk        : in STD_LOGIC;
           rstn       : in STD_LOGIC;
           load : in STD_LOGIC;
           enable : in STD_LOGIC;
           serial_in : in STD_LOGIC;
           parallel_in : in STD_LOGIC_VECTOR(Dbits-1 downto 0);
           dout : out STD_LOGIC;
           parallel_out : out STD_LOGIC_VECTOR(Dbits-1 downto 0)
          );
end component;

signal   serial_clk : STD_LOGIC := '0';
signal   clk        : STD_LOGIC := '0';
signal   rstn       : STD_LOGIC;
signal   load :  STD_LOGIC := '1';
signal   enable :  STD_LOGIC := '0';
signal   serial_in :  STD_LOGIC;
signal   parallel_in :  STD_LOGIC_VECTOR(Dbits-1 downto 0) := (others => '0');
signal   dout :  STD_LOGIC;
signal   parallel_out :  STD_LOGIC_VECTOR(Dbits-1 downto 0);
signal   dout2 :  STD_LOGIC;
signal   parallel_out2 :  STD_LOGIC_VECTOR(Dbits-1 downto 0);

signal end_of_simu : STD_LOGIC := '0';

begin

SR1 : SerDes 
    generic map( 
        Dbits => Dbits
           )  
    Port map(
           serial_clk    => serial_clk,
           clk           => clk,
           rstn          => rstn,
           load          => load,
           enable        => enable,
           serial_in     => dout2,
           parallel_in   => parallel_in,
           dout          => dout,
           parallel_out  => parallel_out
          );

 SR2 : SerDes 
      generic map( 
          Dbits => Dbits
             )  
      Port map(
             serial_clk    => serial_clk,
             clk           => clk,
             rstn          => rstn,
             load          => load,
             enable        => enable,
             serial_in     => dout,
             parallel_in   => parallel_in,
             dout          => dout2,
             parallel_out  => parallel_out2
            );


stimulus : process
  begin
      rstn <= '0';
      wait for 100 ns;
      rstn <= '1';
      wait for 100 ns;
      parallel_in <= X"1234";
      enable <= '1';
      wait;
end process;


clocking : process

begin
  IF end_of_simu /= '1' THEN
      clk <= not clk;
      wait for 5 ns;
  ELSE
      assert false report "end of test" severity note;
      WAIT;
  END IF;
end process;


sclk_gen : process

begin
  IF end_of_simu /= '1' THEN
      serial_clk <= not serial_clk;
      wait for 100 ns;
  ELSE
      assert false report "end of test" severity note;
      WAIT;
  END IF;
end process;

end Behavioral;