VHDL连接不同类型

时间:2018-10-09 07:39:42

标签: type-conversion vhdl concat

我拥有以下现有的FPGA代码

fpga_avr32_data       : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);

SIGNAL read_sensor                       : INTEGER;

TYPE meas_type IS ARRAY (7 DOWNTO 0) OF STD_LOGIC_VECTOR(11 DOWNTO 0);
TYPE meas_reg_type IS ARRAY (NATURAL RANGE <>) OF meas_type;



fpga_avr32_data <= "0000" & meas_reg(read_sensor)(read_channel)

-

我想用read_sensor的最低4个“位”替换“ 0000”,类似这样

fpga_avr32_data <= read_sensor(3 DOWNTO 0) & meas_reg(read_sensor)(read_channel)

这可能吗?

致谢

1 个答案:

答案 0 :(得分:0)

是的,有可能。但不是您的方式。 read_sensor是整数,而fpga_avr32_dataSTD_LOGIC_VECTOR,因此必须首先将整数转换为向量:

library ieee;
use ieee.numeric_std.all;
...
signal rsv: std_logic_vector(31 downto 0);
...
rsv <= std_logic_vector(to_signed(read_sensor, 32));

然后提取4个LSB:

fpga_avr32_data <= rsv(3 DOWNTO 0) & meas_reg(read_sensor)(read_channel);