为什么数组更新会破坏元素值?

时间:2018-10-02 08:47:11

标签: vhdl clash

从CLaSH的输出中简化了以下独立的VHDL文件,这可以解释其有些奇怪的结构。

目的是在s.tup2_sel1(0)s.tup2_sel0的循环中增加"01"。但是,我在VHDL模拟器中看到的是,数组更新后OUTPUT(因此,s.tup2_sel1(0))成为unknoqn(其值为"XXXXXXXX")。为什么数组元素损坏了?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.all;

entity CHIP8 is
  port(-- clock
       CLK    : in std_logic;
       -- asynchronous reset: active high
       RESET  : in std_logic;
       OUTPUT : out unsigned(7 downto 0));

  type array_of_unsigned_8 is array (integer range <>) of unsigned(7 downto 0);

  type tup2 is record
    tup2_sel0 : std_logic_vector(1 downto 0);
    tup2_sel1 : array_of_unsigned_8(0 to 1);
  end record;

end;

architecture structural of CHIP8 is
  signal y1 : array_of_unsigned_8(0 to 1);
  signal s  : tup2;
  signal s1 : tup2;
  signal y  : array_of_unsigned_8(0 to 1);
  signal x  : unsigned(7 downto 0);
begin
  y <= s.tup2_sel1;
  x <= y(0);

  process(y)
    variable ivec : array_of_unsigned_8(0 to 1);
  begin
    ivec := y;
    ivec(0) := x + 1;
    y1 <= ivec;
  end process;

  with s.tup2_sel0 select
    s1 <= (tup2_sel0 => "01", tup2_sel1 => y) when "00",
          (tup2_sel0 => "10", tup2_sel1 => y1) when "01",
          (tup2_sel0 => "10", tup2_sel1 => y) when others;

  process(CLK,RESET)
  begin
    if RESET = '1' then
      s <= (tup2_sel0 => "00", tup2_sel1 => array_of_unsigned_8'(0 to 1 => to_unsigned(0,8)));
    elsif rising_edge(CLK) then
      s <= s1;
    end if;
  end process;

  OUTPUT <= x;
end;

我的顶级测试平台会生成RESET信号:

LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.all;

ENTITY TB IS
END TB;

ARCHITECTURE behavior OF TB IS  
  signal CLK : std_logic := '0';
  signal RESET : std_logic := '0';
  signal OUTPUT : unsigned(7 downto 0);

  constant CLK_period : time := 10 ns; 
BEGIN
  uut: entity work.CHIP8 PORT MAP (
    CLK => CLK,
    RESET => RESET,
    OUTPUT => OUTPUT);

  CLK_proc :process
  begin
    CLK <= '0';
    wait for CLK_period/2;
    CLK <= '1';
    wait for CLK_period/2;
  end process;

  RESET_proc: process
  begin
    RESET <= '1';     
    wait for CLK_period * 2;
    RESET <= '0';
    wait;
  end process;
END;

1 个答案:

答案 0 :(得分:3)

x的敏感度列表中缺少信号process(y)。这可能是有意为之,但在99%的情况下这是一个错误。

因为它是生成的代码,所以我无法确定编写代码发射器的人是否是像我这样的聪明VHDL程序员,因为他们知道敏感度列表是一种语法糖,还是只是错过了向敏感度列表中添加更多信号...

敏感度列表如何翻译?
参见以下示例:

process(y, x)
begin
  -- some code
end process;

已翻译为:

process
begin
  -- some code
  wait on y, x;
end process;

因此,如果他们很聪明,他们可以推测仅对y个事件而不是对'x'个事件进行恢复。一些VHDL专家可能会使用它来优化流程唤醒,其他人则将其称为棘手的代码行。


当信号包含诸如XU-X之类的元值和诸如{{1}之类的算术时,可以生成

W值}。

除重置条件外,我没有看到+ 1的任何初始化值。
那么,您是否在仿真中应用了RESET?