Question

我是Verilog编程的新手，正在致力于使用2个4位比较器实现8位无符号幅度比较器。我相信我的代码已正确实现，但是我收到的错误是由于错误的变量类型分配引起的。因为我是该语言的新手，所以我认为这是一次学习的机会，但是我找不到足够的相关材料来指导我解决问题。如果有人可以解释为什么我使用的类型不正确（或者如果我遇到的是另一个问题），将不胜感激。

编辑：我改变了我对这个建议的回答，模块实例化在Always块和连线之外，分别为eq，gt和lt，但是仍然出现错误。更新了错误代码。

module MagComp4Bit (input [3:0] a, input [3:0] b, output eq, output gt, output lt);

    assign eq = a==b;
    assign gt = a>b;
    assign lt = a<b;

endmodule

module MagComp8Bit (input [7:0] a, input [7:0] b, output eq, output gt, output lt);

    reg eq0, gt0, lt0, eq1, gt1, lt1;

    MagComp4Bit comp1(a[3:0], b[3:0], eq0, gt0, lt0);
    MagComp4Bit comp2(a[7:4], b[7:4], eq1, gt1, lt1);
    always @(a, b)
    begin


            if (eq1) begin
                    eq = eq0? 1 : 0;
                    gt = gt0? 1 : 0;
                    lt = lt0? 1 : 0;
            end
            else begin
                    gt = gt1? 1 : 0;
                    lt = lt1? 1 : 0;
            end
    end
endmodule

module TestComparator;
    reg[7:0] a, b;
    wire eq, gt, lt;

    MagComp8Bit compare(a, b, eq, gt, lt);

    initial begin
            $moniter("%d a=%b, b=%b, eq=%b, gt=%b, lt=%b",
                    $time, a, b, eq, gt, lt);

            #10     a = 2;
                    b = 5;
    end
endmodule

错误消息：

hw1p1.v:13: error: reg eq0; cannot be driven by primitives or continuous 
assignment.
hw1p1.v:13: error: Output port expression must support continuous 
assignment.
hw1p1.v:13:      : Port 3 (eq) of MagComp4Bit is connected to eq0
hw1p1.v:13: error: reg gt0; cannot be driven by primitives or continuous 
assignment.
hw1p1.v:13: error: Output port expression must support continuous 
assignment.
hw1p1.v:13:      : Port 4 (gt) of MagComp4Bit is connected to gt0
hw1p1.v:13: error: reg lt0; cannot be driven by primitives or continuous 
assignment.
hw1p1.v:13: error: Output port expression must support continuous 
assignment.
hw1p1.v:13:      : Port 5 (lt) of MagComp4Bit is connected to lt0
hw1p1.v:14: error: reg eq1; cannot be driven by primitives or continuous 
assignment.
hw1p1.v:14: error: Output port expression must support continuous 
assignment.
hw1p1.v:14:      : Port 3 (eq) of MagComp4Bit is connected to eq1
hw1p1.v:14: error: reg gt1; cannot be driven by primitives or continuous 
assignment.
hw1p1.v:14: error: Output port expression must support continuous 
assignment.
hw1p1.v:14:      : Port 4 (gt) of MagComp4Bit is connected to gt1
hw1p1.v:14: error: reg lt1; cannot be driven by primitives or continuous 
assignment.
hw1p1.v:14: error: Output port expression must support continuous 
assignment.
hw1p1.v:14:      : Port 5 (lt) of MagComp4Bit is connected to lt1
hw1p1.v:22: error: eq is not a valid l-value in TestComparator.compare.
hw1p1.v:9:      : eq is declared here as wire.
hw1p1.v:23: error: gt is not a valid l-value in TestComparator.compare.
hw1p1.v:9:      : gt is declared here as wire.
hw1p1.v:24: error: lt is not a valid l-value in TestComparator.compare.
hw1p1.v:9:      : lt is declared here as wire.
hw1p1.v:27: error: gt is not a valid l-value in TestComparator.compare.
hw1p1.v:9:      : gt is declared here as wire.
hw1p1.v:28: error: lt is not a valid l-value in TestComparator.compare.
hw1p1.v:9:      : lt is declared here as wire.
17 error(s) during elaboration.

（P.S。我知道将测试平台与其他模块一起使用是不适当的，但是当我一次看到所有内容时，对我来说更容易学习。）

Answer 1

Verilog模块不打算在初始块或始终块中实例化。这就是为什么您应该移动：

MagComp4Bit(a[3:0], b[3:0], eq0, gt0, lt0);
MagComp4Bit(a[7:4], b[7:4], eq1, gt1, lt1);

在always块之外的

。而且，eq, gt, lt应该在您的TestComparator模块中声明为导线。

Answer 2

wire类型不能在任何程序块（始终，初始，..）中分配。您正在always

内执行此操作

always...  
    .. 
    eq = eq0? 1 : 0;

其中eq被定义为没有任何数据类型的端口，默认情况下意味着wire。其他两个端口相同：lt和gt。

您需要稍微更改代码：

reg eqReg, ltReg, wrReg;

always @(a, b)
    begin

        if (eq1) begin
                eqReg = eq0? 1 : 0;
                gtReg = gt0? 1 : 0;
                ltReg = lt0? 1 : 0;
        end
        else begin
                gtReg = gt1? 1 : 0;
                ltReg = lt1? 1 : 0;
        end
end
assign eq = eqReg;
assign lt = ltReg;
assign gt = gtReg;

可能由于错误的变量类型而导致的iverilog错误

2 个答案: