STM32H743。 FMC和外部SDRAM。无信号BA0,BA1,UDQM,LDQM

时间:2018-08-20 15:10:26

标签: stm32

我尝试连接STM32H743 MCU和SDRAM(MT48LC16M16A2)。 FMC工作正常,但效果却很差。我检查了信号,发现BA0,BA1,UDQM,LDQM不变(只有LOW电平)。 但!当我写入0x60000000 SDRAM起始地址时,它会生成所有信号,但是我无法写入/读取SDRAM。我没有在FMC_BCR1中重新映射。 重要!同一块板已经过STM32F429测试,并且可以正常工作。

#define SDRAM_START_ADDR ((uint32_t) 0xC0000000)            // SDRAM bank1 area start address

    void fmc_SDRAM_init(void)

{     fmc_SDRAM_GPIOConfig(); //用于SDRAM的初始化GPIO引脚

RCC->D1CCIPR |= (RCC->D1CCIPR & RCC_D1CCIPR_FMCSEL) | RCC_D1CCIPR_FMCSEL_1; // FMC kernel clock source = per_pll2 = 120 MHz
RCC->AHB3ENR |= RCC_AHB3ENR_FMCEN;          // Enable the FMC interface clock

/*
    FMC enable
*/
FMC_Bank1->BTCR[0] &= ~(1 << 31);

FMC_Bank1->BTCR[0] |= (1 << 24);

/* 
    FMC_Bank5_6_R_BASE = SDCR[0]    
    Configure and enable SDRAM bank1 in response to SDRAM datasheet
    SDCLK = 2 x fmc_ker_ck; WP allowed; CAS = 2 Clk; Four internal banks; 
    data bus = 16; Row address bits = 13; column address bits = 9; single read are NOT managed as bursts
*/
FMC_Bank5_6->SDCR[0] = FMC_SDCR1_SDCLK_1 | FMC_SDCR1_CAS_1 | FMC_SDCR1_NB | FMC_SDCR1_MWID_0 | FMC_SDCR1_NR_1 | FMC_SDCR1_NC_0; // init sdram. 0x00000959

/*
    Timming config (all in SDRAM_Clk): 
    WR = 2 (!!! must be >= 4); RC = 4; RAS = 5; XSR = 5; MRD = 3; RCD = 1; RP = 1; 
*/
FMC_Bank5_6->SDTR[0] = FMC_SDTR1_TWR_1 | FMC_SDTR1_TWR_0 | FMC_SDTR1_TRC_1 | FMC_SDTR1_TRC_0 | FMC_SDTR1_TRAS_2 | FMC_SDTR1_TXSR_2 | FMC_SDTR1_TMRD_1; // init timings. 0x00013442

/*
    SDRAM initialization sequence
*/
/*
    Clock enable command
*/
FMC_Bank5_6->SDCMR  = FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_0;// 0x00000011

/*
    Delay = 1000 mks
*/
HAL_Delay(1);   

/*
    All Bank Precharge command
*/
FMC_Bank5_6->SDCMR = FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_1;
{
    // wait at least RP time = 15 ns (min)
    int timeRP = 8; // t_clk = 1/400MHz = 2.5 ns => 8 cycles
    while ((--timeRP))
        continue;
}
HAL_Delay(1);   

/*
    Auto refresh command (NRFS = TRC in SDCR1 register)
*/
FMC_Bank5_6->SDCMR = FMC_SDCMR_NRFS_1 | FMC_SDCMR_NRFS_0 | FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_1 | FMC_SDCMR_MODE_0;// 0x00000073;
{
    // wait at least RFC time = 66 ns (min)
    int timeRP = 30;    // t_clk = 1/400MHz = 2.5 ns => 30 cycles
    while ((--timeRP))
        continue;
}


/*
    MRD register program:
    Mode register bits M[2:0] specify the BL; 
    M3 specifies the type of burst; M[6:4] specify the CL; 
    M7 and M8 specify the operating mode; 
    M9 specifies the write burst mode; and M10–Mn should be set to zero to ensure compatibility with future revisions. 
    Mn + 1 andMn + 2 should be set to zero to select the mode register.

    Mode Register = 0b0000 0100 0100 0 (CL = 2; M9 - Single Location Access)
*/
FMC_Bank5_6->SDCMR = 0x00044000 | FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_2; // 0x00044014
{
    // wait at least MRD time = 3 Clk
    int timeRP = 30;    // 3 cycles
    while ((--timeRP))
        continue;
}

/*
    Set refresh count
*/
FMC_Bank5_6->SDRTR = (FMC_Bank5_6->SDRTR & FMC_SDRTR_REIE) | (0x000001EF << 1);



/*
    FMC enable
*/
HAL_Delay(100); 
FMC_Bank1->BTCR[0] |= (1 << 31);

}

在main.c中:

fmc_SDRAM_init();

while(1)
{
    HAL_Delay(500);
    Address = SDRAM_START_ADDR + 2;
    Pattern = 0xAAAA;
    MemTest_WriteReadSDRAM(Address, Pattern, dbw16Bit);

    Address = SDRAM_START_ADDR + 0x4000;
    Pattern = 0xAAAA;
    MemTest_WriteReadSDRAM(Address, Pattern, dbw16Bit);

    Address = SDRAM_START_ADDR + 0x8000;
    Pattern = 0xAAAA;
    MemTest_WriteReadSDRAM(Address, Pattern, dbw16Bit);

    Address = SDRAM_START_ADDR + 0xC000;
    Pattern = 0xAAAA;
    MemTest_WriteReadSDRAM(Address, Pattern, dbw16Bit);

}

}

示意图:

CPU SDRAM

有人可以帮助我吗?

谢谢!

0 个答案:

没有答案