移位加法乘法函数产生语法错误

Question

我有一些代码如下：

module trapverilog(
    input CLK,
     input signed [7:0] SIGNAL,
     input signed [7:0] x,
     input signed [7:0] SUM, // OUT pins are mapped to SUM pins on board
    output reg OUTP,
     output reg OUT1,
     output reg OUT2,
     output reg OUT3,
     output reg OUT4,
     output reg OUT5,
     output reg OUT6,
     output reg OUT7
    );

reg[7:0] yregone;
reg[7:0] yregtwo;
reg[7:0] innerSumOutput;
reg[7:0] innerSignal;
reg[7:0] innerSum;

function [7:0] multiply;
input [7:0] a;
input [7:0] b;
wire [15:0] a1, a2, a3, a4, a5, a6, a7, a8;
assign a1 = (b[0]==1'b1) ? {8'b00000000, a} : 16'b0000000000000000;
assign a2 = (b[1]==1'b1) ? {7'b0000000, a, 1'b0} : 16'b0000000000000000;
assign a3 = (b[2]==1'b1) ? {6'b000000, a, 2'b00} : 16'b0000000000000000;
assign a4 = (b[3]==1'b1) ? {5'b00000, a, 3'b000} : 16'b0000000000000000;
assign a5 = (b[4]==1'b1) ? {4'b0000, a, 4'b0000} : 16'b0000000000000000;
assign a6 = (b[5]==1'b1) ? {3'b000, a, 5'b00000} : 16'b0000000000000000;
assign a7 = (b[6]==1'b1) ? {2'b00, a, 6'b000000} : 16'b0000000000000000;
assign a8 = (b[7]==1'b1) ? {1'b0, a, 7'b0000000} : 16'b0000000000000000;
multiply = a1 + a2 + a3 + a4 + a5 + a6 + a7 + a8;
endfunction

always @(posedge CLK)
begin
    yregtwo <= yregone;
    yregone <= innerSignal;

    if (yregone != 0)
    begin
        innerSum <= multiply((yregone + yregtwo), x); //treats x as plain h, change if treated as h/2 // multiply defined by function shift-adds
        innerSumOutput <= (innerSum <<< 1) + innerSum; // <<< is signed one bit shift which = /2
        if (innerSumOutput[0] == 1)
        begin
            OUTP <= 1;
        end

        OUT1 <= innerSumOutput[1];
        OUT2 <= innerSumOutput[2];
        OUT3 <= innerSumOutput[3];
        OUT4 <= innerSumOutput[4];
        OUT5 <= innerSumOutput[5];
        OUT6 <= innerSumOutput[6];
        OUT7 <= innerSumOutput[7];
    end
end

endmodule

代码的基本目的是执行梯形积分方法。直到我添加了multiply函数（该函数是移位加乘函数）之前，代码一直进行编译。我进行了更改，因为在聊天中被告知*在FPGA上无法正常工作。我读了一点，发现了这种方法，但是那很可能是一个X-Y问题。

我改编了我发现的this module中的函数，然后按照示例here将其更改为函数。程序产生的错误看起来像是一些语法错误，加上对“过程连续赋值”的抱怨：

ERROR:HDLCompiler:806 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 45: Syntax error near "wire".
ERROR:HDLCompiler:1366 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 42: Multiple statement function/task without begin/end not supported in this mode of Verilog
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 46: <a1> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 46: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 47: <a2> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 47: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 48: <a3> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 48: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 49: <a4> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 49: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 50: <a5> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 50: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 51: <a6> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 51: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 52: <a7> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 52: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 53: <a8> is not declared.
ERROR:HDLCompiler:1673 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 53: Automatic variable a is not allowed in procedural continuous assignments
ERROR:HDLCompiler:69 - "/home/ise/FPGA/trapezoid/trapverilog.v" Line 54: <a1> is not declared.

我对Verilog进行编程还很陌生，并且不确定是什么问题。我也不确定这是否适用于带签名的号码。任何帮助，将不胜感激。谢谢！

Answer 1

您不能在函数内声明<android.support.v7.widget.Toolbar android:id="@+id/toolBar" android:layout_width="match_parent" android:layout_height="?attr/actionBarSize" android:background="?attr/colorPrimary" app:contentInsetEnd="0dp" app:contentInsetLeft="0dp" app:contentInsetRight="0dp" app:contentInsetStart="0dp" app:popupTheme="@style/AppTheme.PopupOverlay"> <RelativeLayout android:layout_width="match_parent" android:layout_height="match_parent"> <LinearLayout android:id="@+id/llLeft" android:layout_width="wrap_content" android:layout_height="match_parent" android:layout_alignParentLeft="true" android:layout_alignParentStart="true" android:background="@drawable/transparent_layout_background" android:clickable="true" android:focusable="true" android:gravity="center" android:padding="10dp"> <ImageView android:id="@+id/ivLeft" android:layout_width="wrap_content" android:layout_height="wrap_content" android:adjustViewBounds="true" android:src="@drawable/ic_action_menu" /> </LinearLayout> <LinearLayout android:layout_width="match_parent" android:layout_height="match_parent" android:layout_toEndOf="@+id/llLeft" android:layout_toLeftOf="@+id/llRight" android:layout_toRightOf="@+id/llLeft" android:layout_toStartOf="@+id/llRight" android:gravity="center"> <TextView android:id="@+id/tvTitle" android:layout_width="wrap_content" android:layout_height="wrap_content" android:ellipsize="end" android:fontFamily="@font/roboto_bold" android:lines="1" android:text="asdf" android:textColor="@color/colorWhite" android:textSize="18sp" /> </LinearLayout> <LinearLayout android:id="@+id/llRight" android:layout_width="wrap_content" android:layout_height="match_parent" android:layout_alignParentEnd="true" android:layout_alignParentRight="true" android:background="@drawable/transparent_layout_background" android:clickable="true" android:focusable="true" android:gravity="center" android:padding="10dp"> <ImageView android:id="@+id/ivRight" android:layout_width="wrap_content" android:layout_height="wrap_content" android:adjustViewBounds="true" android:src="@drawable/ic_action_search" /> </LinearLayout> </RelativeLayout> </android.support.v7.widget.Toolbar> 。请改用wire。

请勿在函数内部使用reg。

有关assign和wire之间的区别的更多详细信息，请参见my blog。