我编写了一个VHDL函数vectorize()
,将std_logic_vector(在我的代码中为slv_1d_array_type
类型)的数组转换为std_logic_vector。
Vivado 2018.2使用以下示例生成此错误[Synth 8-5882] found unsupported attribute ["test_top.vhd":41]
。我已将Vivado配置为使用VHDL-2008。
如何使这些'length
属性起作用,以避免传递数组大小?
-- Libraries
------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------------------------------------------------------
-- Entity
------------------------------------------------------------------------------------------------------------------------
entity test_top is
generic(
DATA_WIDTH : positive := 32
);
port(
O_DATA : out std_logic_vector(DATA_WIDTH - 1 downto 0)
);
end entity test_top;
------------------------------------------------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------------------------------------------------
architecture rtl of test_top is
--------------------------------------------------------------------------------------------------------------------
-- Types definition
--------------------------------------------------------------------------------------------------------------------
type slv_1d_array_type is array (natural range <>) of std_logic_vector; -- One-dimensional std_logic_vector array type.
--------------------------------------------------------------------------------------------------------------------
-- Functions declaration
--------------------------------------------------------------------------------------------------------------------
function vectorize(constant SLV_1D_ARRAY : in slv_1d_array_type) return std_logic_vector is
variable vector_v : std_logic_vector(SLV_1D_ARRAY'length * SLV_1D_ARRAY'element'length - 1 downto 0);
begin
for i in SLV_1D_ARRAY'range loop
vector_v(SLV_1D_ARRAY'element'length * (i + 1) - 1 downto SLV_1D_ARRAY'element'length * i) := SLV_1D_ARRAY(i);
end loop;
return vector_v;
end function vectorize;
--------------------------------------------------------------------------------------------------------------------
-- Signals declaration
--------------------------------------------------------------------------------------------------------------------
signal data_r : slv_1d_array_type(0 to DATA_WIDTH / 8 - 1)(7 downto 0) := (others => (others => '0'));
begin
O_DATA <= vectorize(data_r);
end architecture rtl;
答案 0 :(得分:2)
根据第6章“ VHDL-2008语言支持”中的UG901,没有提到'element
属性。因此它不受官方支持。
Xilinx论坛上的此thread表示该版本受到严重支持,并且已从Vivado 2016.3。开始删除。
但是,上面的代码示例已被ModelSim 10.6c接受。
@Juergen提供的解决方案正在Vivado 2018.2。中正常工作。这是该示例的更新版本,包括解决方法:
-- Libraries
------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------------------------------------------------------
-- Entity
------------------------------------------------------------------------------------------------------------------------
entity test_top is
generic(
DATA_WIDTH : positive := 32
);
port(
O_DATA : out std_logic_vector(DATA_WIDTH - 1 downto 0)
);
end entity test_top;
------------------------------------------------------------------------------------------------------------------------
-- Architecture
------------------------------------------------------------------------------------------------------------------------
architecture rtl of test_top is
--------------------------------------------------------------------------------------------------------------------
-- Types definition
--------------------------------------------------------------------------------------------------------------------
type slv_1d_array_type is array (natural range <>) of std_logic_vector; -- One-dimensional std_logic_vector array type.
--------------------------------------------------------------------------------------------------------------------
-- Functions declaration
--------------------------------------------------------------------------------------------------------------------
function vectorize(constant SLV_1D_ARRAY : in slv_1d_array_type) return std_logic_vector is
variable vector_v : std_logic_vector(SLV_1D_ARRAY'length * SLV_1D_ARRAY(SLV_1D_ARRAY'low)'length - 1 downto 0);
begin
for i in SLV_1D_ARRAY'range loop
vector_v(SLV_1D_ARRAY(SLV_1D_ARRAY'low)'length * (i + 1) - 1 downto SLV_1D_ARRAY(SLV_1D_ARRAY'low)'length * i) := SLV_1D_ARRAY(i);
end loop;
return vector_v;
end function vectorize;
--------------------------------------------------------------------------------------------------------------------
-- Signals declaration
--------------------------------------------------------------------------------------------------------------------
signal data_r : slv_1d_array_type(0 to DATA_WIDTH / 8 - 1)(7 downto 0) := (others => (others => '0'));
begin
O_DATA <= vectorize(data_r);
end architecture rtl;