Question

我有一个简单的通用单时钟ram，它有多个通用值。但是，我在声明时遇到语法错误。代码的完整结构是：

entity main is
Port ( 
-- components
);
end main;


architecture Behavioral of main is
component xilinx_simple_dual_port_1_clock_ram is 
    generic (
    RAM_WIDTH : integer, --< what is wrong here?
    RAM_DEPTH : integer,
    RAM_PERFORMANCE : string,
    INIT_FILE : string
    );
port 
    (
    addra : in std_logic_vector(clogb2(RAM_DEPTH)-1) downto 0);
    addrb : in std_logic_vector(clogb2(RAM_DEPTH)-1) downto 0); 
    dina  : in std_logic_vector(RAM_WIDTH-1 downto 0);
    clka  : in std_logic;
    wea   : in std_logic;
    enb   : in std_logic;
    rstb  : in std_logic;
    regceb: in std_logic;
    doutb : out std_logic_vector(RAM_WIDTH-1 downto 0)
    );

    end component;

begin
ramA: xilinx_simple_dual_port_1_clock_ram
     generic map (
     RAM_WIDTH => 18,
     RAM_DEPTH => 1024,
     RAM_PERFORMANCE => "HIGH_PERFORMANCE",
     INIT_FILE => "" 
    )
      port map  (
     addra  => addra, 
     addrb  => addrb, 
     dina   => dina,  
     clka   => clka,  
     wea    => wea,   
     enb    => enb,   
     rsta   => rsta,  
     regceb => regceb,
     doutb  => doutb 
    );

已经处理了其他信号，包括映射到bram模块的端口。我在泛型声明中遇到语法错误。

Answer 1

您必须为通用提供默认值：

RAM_WIDTH : integer := 16;
--                       ^

同时使用;而不是,

VHDL通用组件声明语法错误

1 个答案: