Vhdl，有没有办法，在大于64位的无符号上使用modulo？

Question

我有两个115位无符号向量。我必须对它们进行一些模拟计算，但Quartus会显示这些错误。

Error: In lpm_divide megafunction, LPM_WIDTHN must be less than or equals to 64
Error: In lpm_divide megafunction, LPM_WIDTHD must be less than or equal to 64
Error: Can't elaborate inferred hierarchy "lpm_divide:Mod0"

我完全理解，这些数字太大而无法执行mod。有没有办法/图书馆/任何想法如何解决这个问题？我希望避免使用任何＆＃34;减法循环＆＃34;，并尽可能简单。 VHDL不是我的世界，在学术项目之后我会高兴地放弃它：P

应用程序必须计算模数反转。至于我不是VHDL的主人，我已经尝试过使用快速供电+ mod alghoritm。应用程序很糟糕，只需要工作：d

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.altera_primitives_components.all;

entity inwersja is
    port(
        a: in unsigned(114 downto 0);
        clk: in std_logic;
        start: in std_logic;
        reset: in std_logic;
        c: out unsigned(114 downto 0);
        ready: out std_logic);
    end inwersja;


architecture i1 of inwersja is
    begin
    process(clk)
        variable tempOutput : unsigned(114 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
        variable temp : unsigned (114 downto 0):= a;
        variable modul: unsigned(114 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101011";
        variable power: unsigned(114 downto 0) := "1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101001";
        variable counter: integer := 0;
        begin
            if reset='1' then
                tempOutput := "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
                ready <= '0';
            elsif clk'event and clk='1' then
                if start='0' then
                    ready<='0';
                else
                    if (counter < 115) then
                        if (power(counter) /= '0') then
                            tempOutput := (tempOutput * temp) mod modul;
                        end if;
                        temp := (temp * temp) mod modul;

                        counter := counter + 1;
                    elsif (counter = 115) then
                        ready <= '1';
                    end if;
                end if;
            end if;
            c <= tempOutput;
    end process;
end i1;