Question

这是我第一次使用rtl，所以我遇到了一些可能很简单的问题，但是我找不到任何可以解释为什么会发生这种情况的问题以及如何解决它。目前，当我从我的vhdl代码创建一个rtl时，输出不会显示为连接到设计的其余部分。下图显示了输出，而不是设计的其余部分，因为它非常大。

我的代码中相关的部分可以在下面看到：

`library IEEE;

 use IEEE.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
 use ieee.std_logic_arith.all;
 use ieee.numeric_std.all;

 entity FIFOClockOut is
port (
    --Inputs
    dataIn      :   IN  std_logic_vector(7 downto 0);       -- data input
    clk         :   IN  std_logic;                          -- clock input
    EnableWr    :   IN  std_logic;                          -- a value is being transmitted to the FIFO
    clearMem    :   IN  std_logic;                          -- clears the memory of the FIFO
    resetOut    :   IN  std_logic;                          -- resets the FIFO output counter
    resetFull   :   IN  std_logic;                          -- resets the the FIFO completely
    --Outputs
MemNear     :   INOUT std_logic;            -- the memory is almost out
    FullMem     :   OUT std_logic;                          -- the memory is full in the FIFO
    dataOut     :   OUT std_logic_vector(7 downto 0);     -- data output
    sel         :   INOUT std_logic_vector(2 downto 0);     -- select output for mux
    FinishedOut :   OUT std_logic;                  -- the FIFO has finished sending out the data
clkOut      :   INOUT std_logic := '0'          -- the clock that the output data is using
);
 end FIFOClockOut;

  architecture architecture_FIFOClockOut of FIFOClockOut is
  -- signal, component etc. declarations
  type ram_t is array (0 to 4095) of std_logic_vector(7 downto 0);                -- The memory for the FIFO
signal ram: ram_t;
signal counterIn    : integer;                -- counter for input
signal counterOut   : integer;                -- counter for output
signal counterClock : std_logic_vector(2 downto 0);                -- counter for clock
signal FullMemBuff  : std_logic;
signal FinishedOutBuff: std_logic;
begin
process(clk)
begin
--there is some more code here which does not use dataOut
if (clk='1') then
    if (FullMemBuff = '0') then 
        if (EnableWr = '1') then
                ram(counterIn)<= dataIn;
                counterIn   <= counterIn + 1;
                end if;
            end if;
if(clkOut ='1') then
    if (FinishedOutBuff = '0') then
            counterClock <= counterClock + "1";
                sel     <= sel+"1";
                end if;
    if (counterClock = "111") then
            if (FinishedOutBuff = '0') then
                    dataOut       <=  ram(counterOut);
                    counterOut    <=  counterOut+1;
            if (counterIn <= (counterOut)) then
                FinishedOutBuff <= '1';
                sel<= "111";
                dataOut <= "00000000";
                end if;     
            else
            dataOut      <=   "00000000";
            sel          <=   "111";
            end if;
                end if;
    end if;
    end if;

   end process;
   end architecture_FIFOClockOut;

感谢您的帮助。我正在使用Libero Polar Fire来编码vhdl并创建rtl。我已经模拟了代码，它按预期工作，并提供正确的输出。如果不清楚或想要更多代码，请提问。

Answer 1

所以我通过在代码的开头添加一个缓冲信号并将DataOut值设置为等于DataOut缓冲区来解决这个问题。不太确定为什么会这样，但它修复了它。如果有人知道为什么我想知道。

输出未连接到rtl中的其余设计

1 个答案: