Question

我有一个用于传输触发架构处理器的 MAC 单元，但出于某种原因。乘法累加部分不起作用。我单独测试了它并且它有效，但是当模拟时out_reg_int始终是0，即使op_a和op_b是正确的值，我已经包含Numeric_STD。

-- These are just for the question
num_in_reg := 2;
num_reg := 4;
data_size := 71;
data_width := 64;

SIGNAL op_a, op_b : SIGNED(data_width-1 DOWNTO 0);
Signal out_reg_int, out_reg_out_int : SIGNED((data_width*2)-1 DOWNTO 0);

TYPE bus_array3 IS ARRAY (num_reg-1 DOWNTO num_in_reg) OF Signed(data_width-1 DOWNTO 0);
SIGNAL out_reg_in: bus_array3; -- for output register inputs
SIGNAL result: bus_array3; -- for results

op_a <= SIGNED(reg_out(0)(data_width-1 DOWNTO 0)); -- operand A
op_b <= SIGNED(reg_out(1)(data_width-1 DOWNTO 0)); -- operand B (trigger register)

-- Multiply Accumulate Operation
out_reg_int <= (op_a * op_b) + out_reg_out_int; -- multiply operands and add to current result

out_reg_out_int <= result(3) & result(2); -- combining the output registers lower and higher parts

out_reg_in(2) <= out_reg_int(data_width-1 downto 0); -- lower part of the result
out_reg_in(3) <= out_reg_int((data_width*2)-1 downto data_width); -- upper part of the result

------------------------------------------------------
-- Basically a register for pre place and route simulation.
------------------------------------------------------
result_regs: FOR J IN num_in_reg TO num_reg-1 GENERATE
Razor_result : entity work.Razor(Behavioral)
Generic Map (data_size => data_width)
Port Map (clk => CLK,
             rst => Test_rst,
             data => std_logic_vector(out_reg_in(J)),
             wen => out_reg_en(J),
             signed(data_out) => result(J),
             error => Razor_error_int(J));   
End Generate;

在测试平台中，op_a为x64，op_b为x100且out_reg_int，out_reg_in和out_reg_out_int均为{ {1}}。

该单位的完整代码是This：

乘积累加单位

0 个答案: