Question

我试图测试我的VHDL代码，例如：

entity fulladder4bit is
    port( a,b,cin: in std_logic;
          s,cout: out std_logic);
end fulladder4bit;

architecture FA4 of fulladder4bit is
    signal p,g: std_logic;
begin
    p<= a xor b;
    g<= a and b;
    s<= p xor cin;
    cout<= g or (p and cin);
end FA4;

所以我写了这个测试平台：

entity fulladd4_testbench is
end fulladd4_testbench;

architecture FA4_TB of fulladd4_testbench is
    component fulladder4bit is
        port( a,b,cin: in bit;
              s,cout: out bit);
    end component;

    signal iA: bit;
    signal iB: bit;
    signal iCin: bit;
    signal oS: bit;
    signal oCout: bit;

begin
    fa4: fulladder4bit port map(iA, iB, iCin, oS, oCout);

process
    begin
        iA<='1';
        iB<='1';
        iCin<='0';    
end process;
end FA4_TB;

end FA4_TB;

我遵循了一个教程（由我的老师发布），然后我点击了Run Synthesis，然后运行模拟，但是模拟加载永远不会结束，现在我按下取消，但是这个加载永远不会结束！我犯了一些错误吗？

我正在使用Vivado

模拟加载永远不会在Vivado上结束

0 个答案: