Question

如何在保持计数功能的同时使用此verilog代码生成1Hz时钟信号？ Maxval使计数器能够计数到某个值，然后通过复位返回到0并重新开始。或者，它只会重置并重新计数，如果它达到最大值。问题是，我的FPGA有50Mhz时钟，但我需要使用1Hz和2Hz时钟的计数器。有关使用此代码进行调整的任何提示吗？

module clocktime(input clk, freerun, Reset, output, input[7:0] Maxval, output reg[7:0] Count, output reg Carry);
    always @ (posedge clk or posedge Reset) begin
        if ( Reset ) begin
            Count <= 0;
            Carry <= 0;
            end
        else
            if ( freerun )
                if ( Count < Maxval ) begin
                    Count <= Count + 8'd1;
                    Carry <= 0;
                    end
                else begin
                    Count <= 0;
                    Carry <= 1;
                    end
        end
endmodule

Answer 1

首先增加Maxval和Count变量的宽度。你需要26位来容纳5000万的数字。现在有8位，你最多可以将时钟除以255。

要获得额外的输出（1hz，2hz），您可以执行以下操作：

module top(clk50, reset, out_1hz, out_2hz);
input clk50;
input reset;
output out_1hz;
output out_2hz;

reg[25:0] clk50_divisor = 12500000;
reg [1:0] div2_4;

assign out_1hz = div2_4[1];
assign out_2hz = div2_4[0];

wire tmp_4hz;

clocktime div_clk50(
    .clk(clk50),
    .freerun(1),
    .Reset(reset), 
    .Maxval(clk50_divisor),
    .Carry(tmp_4hz));


always @(posedge tmp_4hz)
    div2_4 <= div2_4 + 1'd1;

/* another option, might be better in your particular case,
   or not different at all

always @(posedge clk50)
if (tmp_4hz)
   div2_4 <= div2_4 + 1'd1;

*/

endmodule

module clocktime(clk, freerun, Reset, Maxval, Count, Carry);

input clk;
input freerun;
input Reset;
input [25:0] Maxval;
output reg[25:0] Count;
output reg Carry;

    always @ (posedge clk or posedge Reset) begin
        if ( Reset ) begin
            Count <= 0;
            Carry <= 0;
            end
        else
            if ( freerun )
                if ( Count < Maxval ) begin
                    Count <= Count + 8'd1;
                    Carry <= 0;
                    end
                else begin
                    Count <= 0;
                    Carry <= 1;
                    end
        end

endmodule

Verilog计数器 - 50MHz至1Hz时钟

1 个答案: