Question

我想创建验证输出是否正确的任务。如果正确则显示正确的+1，如果出现错误则显示错误+1。通过编写此代码，我无法在expected123中获得任何值。

logic [31:0] expected123;
task checker123 (logic [31:0] expected, logic [31:0] actual, bit [3:0] command, logic[31:0] input1, input2);
  $display("%h, %h, %h, %h, %h", expected, actual, command, input1, input2); 

  if(command == "0001")
    expected123 = input1 + input2;
  $display(expected, input1, input2);

  if(command == "0010")
    expected123 = input1 - input2;
  $display(expected, input1, input2);

  expected = expected123;

  if (expected !== actual) begin
    $display("%t: command %h is expected %h but got %h ", $time, command, expected, actual);
    error = error + 1;
  end
  correct = correct + 1;
endtask

Answer 1

您可能无意中在Verilog中编写了VHDL语法。应该是

  if(command == 4'b0001)

检查数据是否正确的语法（systemverilog）

1 个答案: