这个错误的原因是什么，我该如何解决？

Question

  --------------------------alu.vhd----------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY alu IS 
 PORT( a,b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         cin: IN STD_LOGIC;
         sel: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
         y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END alu;
ARCHITECTURE alu OF alu IS
COMPONENT arith_unit IS 
  PORT( a,b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        cin: IN STD_LOGIC;
          sel: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
          x: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
  );
END COMPONENT;
COMPONENT logic_unit IS 
  PORT( a,b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
          sel: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
          x: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
  );
END COMPONENT;

COMPONENT mux IS 
  PORT( a,b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
          sel: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
          x: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
  );
END COMPONENT;

SIGNAL x1,x2: STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN 
 U1: arith_unit PORT MAP(a,b,cin,sel(2 DOWNTO 0),x1);
 U2: logic_unit PORT MAP(a,b,sel(2 DOWNTO 0),x2);
 U3: mux PORT MAP(a=>x1,b=>x2,sel(3),y);
END alu;

-----------------------------------arith.vhd-----------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY arith_unit IS 
    PORT ( a,b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
             sel: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
             cin : IN STD_LOGIC;
             x: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
    );
END arith_unit;
ARCHITECTURE arith_unit OF arith_unit IS
    SIGNAL arith, logic: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
    WITH sel SELECT
        x<= a WHEN "000",
            a+1 WHEN "001",
             a-1 WHEN "011",
             b+1 WHEN "100",
             b-1 WHEN "101",
             a+b WHEN "110",
             a+b+cin WHEN OTHERS;
END arith_unit;

-----------------------------------logic.vhd--------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY logic_unit IS 
    PORT (a,b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
            sel:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
            x: OUT std_LOGIC_VECTOR(7 DOWNTO 0)
    );
END logic_unit;
ARCHITECTURE logic_unit OF logic_unit IS 
BEGIN 
 WITH sel SELECT 
    x <= NOT a WHEN "000",
          NOT b WHEN "001",
          a AND b WHEN "010",
          a OR b WHEN "011",
          a NAND b WHEN "100",
          a NOR b WHEN "101",
          a XOR b WHEN "110",
          NOT (a XOR b) WHEN OTHERS;
END logic_unit;
------------------mux.vhd--------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY mux IS
 PORT(
        a,b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        sel : IN STD_LOGIC;
        x: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
 );
 END mux;
 ARCHITECTURE mux OF mux IS
 BEGIN 
    WITH sel SELECT
     x<= a WHEN '0',
          b WHEN OTHERS;
END mux;

U3：mux PORT MAP（a =＆gt; x1，b =＆gt; x2，sel（3），y）;创建组件是错误的。

  

错误（10437）：alu.vhd（37）处的VHDL关联列表错误：   必须在命名关联之前列出位置关联。

我该如何解决？