Question

我想使用Vivado在Basys3板上制作一个4位计数器。我在verilog中为它编写了一个代码。我无法生成比特流。我已经粘贴了stopwatch.v模块和约束文件。 Basys3的板载时钟速度为100MHz。

//`timescale 1ns/1ps

module stopwatch( input clk, input reset, input start, input pause, output reg [3:0] out);

   reg [26:0] clock;
   reg        starter;


   always @(posedge clk or posedge reset)
     begin
    if (reset)
      begin
         out <= 0;
         clock <= 0;
      end

    else if (starter)
      begin
         if (clock == 25'd10000000)
           begin
          out <= out + 1'b1;
          clock <= 0;
           end
         else
             clock <= clock + 1'b1;
      end
     end // always @ (posedge clk or posedge reset)

   always @(*)
     begin
    if (start)
      starter <= 1'b1;
    else if (pause)
      starter <= 0;

     end

endmodule // stopwatch

Constraint_file.xdc

set_property PACKAGE_PIN U18 [get_ports {reset}]
set_property PACKAGE_PIN T18 [get_ports {start}]
set_property PACKAGE_PIN U17 [get_ports {pause}]
set_property PACKAGE_PIN U16 [get_ports {out[0]}]
set_property PACKAGE_PIN E19 [get_ports {out[1]}]
set_property PACKAGE_PIN U19 [get_ports {out[2]}]
set_property PACKAGE_PIN V19 [get_ports {out[3]}]



    set_property PACKAGE_PIN W5 [get_ports clk] 
    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports {reset start pause out}]

以下是我一直得到的错误：

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pause_IBUF] >

    pause_IBUF_inst (IBUF.O) is locked to IOB_X0Y14
     and pause_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0

Answer 1

这些工具抱怨您选择“暂停”I / O缓冲区它表示你应该为该信号使用全局时钟缓冲输入（BUFG）。它通过全局时钟缓冲区“BUFGCTRL_X0Y0”路由信号。

这可能与'starter'是一个锁存器的事实有关，而Vivado认为你的暂停信号是一个时钟。这段代码错了：

always @(*)
begin
if (start)
  starter <= 1'b1;
else if (pause)
  starter <= 0;
end

首先：在一个总是组合的块中，你不使用非阻塞分配。你用'='
其次：没有关闭'其他'，所以你得到一个锁。

或者这是你想要的代码：

assign starter = start & ~pause;

另外，您可以将该代码原样移动到您的时钟部分。在这种情况下，请确保您也重置“启动器”。

Basys3板4位计数器，我不知道它为什么不产生比特流？实施错误

1 个答案: