Question

我有一个响铃计数器，它有一个启用和计数启用。碰巧在我的大型设计中，计数使能与时钟同步（我的意思是控制它的电路在上升沿拉回到0）。

观察：

F0和F1输出应在t = 130 ns时发生的上升沿发生变化。但是，count_en输入在环形计数器读取的同时被拉低。

如何从VHDL获取正确的行为？这是我的代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ring_counter_top is
    Port ( CLK      : in  STD_LOGIC;
              RING_EN   : in  STD_LOGIC;
              COUNT_EN  : in  STD_LOGIC;
           F0           : out STD_LOGIC;
              F1            : OUT STD_LOGIC
             );

end ring_counter_top;

architecture Behavioral of ring_counter_top is
    signal shift_reg : STD_LOGIC_VECTOR(1 downto 0) := "01";
     signal F0_temp : STD_LOGIC := '1';
     signal F1_temp : STD_LOGIC := '0';
     signal count_tmp : std_logic;
begin

     count_tmp <= COUNT_EN;
    -- ring counter
    process (CLK, RING_EN, COUNT_EN)
    begin
     if (RISING_EDGE(CLK)) then
          if (count_tmp = '1') then 
                shift_reg(1) <= shift_reg(0);
                shift_reg(0) <= shift_reg(1);
                F0_temp <= shift_reg(0);
                F1_temp <= shift_reg(1);
          end if;
     end if;
    end process;

     F0 <= F0_temp and RING_EN;
     F1 <= F1_temp and RING_EN;

end Behavioral;

Answer 1

代码完全符合它的描述：

在var app = angular.module('app', []); app.controller('myController', function($scope){ $scope.valid = false; $scope.submit = function(){ $scope.valid = true; } $scope.close = function(){ $scope.valid = false; } });的上升沿：

将Trying to validate start and end time shud not be > than 1 hr.USing angular basic functionality for this validation. Also trying to have date-picker but not happening for me as i am on private network. <!DOCTYPE html> <html lang="en" ng-app="app"> <head> <meta charset="utf-8"> <title>AngularJS Form Validation</title> <link href="https://maxcdn.bootstrapcdn.com/bootstrap/3.3.7/css/bootstrap.min.css" rel="stylesheet"> <script src="http://ajax.googleapis.com/ajax/libs/angularjs/1.5.7/angular.min.js"></script> <style type="text/css"> .errortext { color: red; } </style> </head> // form start here <body ng-controller="myController"> <div class="container-fluid"> <div class="row col-md-6 col-sm-6 col-xs-12"> <div class=" form-body"> <form role="form" name="myForm" novalidate> <div class="form-group"> <label class="control-label "> Gate Open Date </label> <div class="input-group"> <input name="gateOpenDate" class="form-control" placeholder="YYYY-MM-DD" ng-pattern="/(\d{4})-(\d{2})-(\d{2})/" ng-model="addFlood.gateOpenDate" required autofocus/> <div class="errortext" ng-show="myForm.gateOpenDate.$dirty && myForm.gateOpenDate.$invalid"> <span ng-show="myForm.gateOpenDate.$error.required">Gate Open Date is required</span> <span ng-show="myForm.gateOpenDate.$error.pattern">Date Format Must Be DD/MM/YYYY</span> </div> <div class="input-group-addon"> <i class="fa fa-calendar"> </i> </div> </div> </div> <div class="form-group " > <label class="control-label "> Start Time </label> <div class="input-group"> <input type="time" name="startTime" class="form-control" placeholder="HH:MM 24h format" ng-model="addFlood.startTime" required/> <div class="errortext" ng-show="myForm.startTime.$dirty && myForm.startTime.$invalid"> <span ng-show="myForm.startTime.$error.required">Start Time is required</span> <span ng-show="myForm.startTime.$error.time">Invalid Time Format</span> </div> <div class="input-group-addon"> <i class="fa fa-clock-o"> </i> </div> </div> </div> <div class="form-group " > <label class="control-label ">End time </label> <div class="input-group"> <input type="time" name="endTime" class="form-control" placeholder="HH:MM 24h format" ng-model="addFlood.endTime" required/> <div class="errortext" ng-show="myForm.endTime.$dirty && myForm.endTime.$invalid || myForm.endTime.$dirty && ((addFlood.endTime-addFlood.startTime)/(1000*60*60) >1)"> <span ng-show="myForm.endTime.$error.required">End Time is required</span> <span ng-show="myForm.endTime.$error.time">Invalid Time Format</span> <span ng-show="!myForm.endTime.$error.required && ((addFlood.endTime-addFlood.startTime)/(1000*60*60)>1)">Flood interval is greater than 1 Hr</span> </div> <div class="input-group-addon"> <i class="fa fa-clock-o"> </i> </div> </div> </div> <div class="form-group "> <label class="control-label "> Number Of Orders </label> <input class="form-control" ng-model="addFlood.numberOfOrders" ng-pattern="/[0-9]+/" name="numberOfOrders" placeholder="Order #" required/> <div class="errortext" ng-show="myForm.numberOfOrders.$dirty && myForm.numberOfOrders.$invalid"> <span ng-show="myForm.numberOfOrders.$error.required">Order Number required</span> <span ng-show="myForm.numberOfOrders.$error.pattern">Only Numbers are Allowed</span> </div> </div> <div class="form-group"> <div> <button class="btn btn-primary " ng-disabled="myForm.$invalid" ng-click="addSdFloodInfo(addFlood, gatingDetil)" name="submit" type="submit"> Submit</button> </div> </div> </div> </form> </div> </div> <script src="angular.js"></script> </body> </html>的值分配给clk和shift_reg(0)
将shift_reg(1)的值分配给F0_temp和shift_reg(1)

您无法更改过程中信号的值（不使用时间延迟，如shift_reg(0)语句）。您只能指示模拟器在下一个增量循环中更改它。

如果确实需要更改流程中的值，则应使用变量而不是信号。 但我非常劝阻，除非你知道你在做什么！如果使用不当，变量可能会在逻辑综合过程中出现问题。

只需对代码进行一些小改动：如果F0_temp和wait切换初始值：

示例代码：

F1_TEMP

编辑：

VHDL模拟器分两个阶段运行：

语句执行，其中评估触发的语句（例如进程语句）并将事件（如信号分配）放入队列中

事件处理，处理队列中的事件。

因此，如果F0_TEMP是一个信号并且您在进程中编写library ieee; use ieee.std_logic_1164.all; entity counter is port ( clk : in std_logic; count_en : in std_logic; f0 : out std_logic; f1 : out std_logic ); end entity; architecture rtl of counter is signal shift_reg : std_logic_vector(1 downto 0) := "01"; signal f0_int : std_logic := '0'; signal f1_int : std_logic := '1'; begin -- ring counter process (clk) begin if rising_edge(clk) then if count_en = '1' then shift_reg <= shift_reg(0)&shift_reg(1); f0_int <= shift_reg(0); f1_int <= shift_reg(1); end if; end if; end process; f0 <= f0_int; f1 <= f1_int; end architecture; library ieee; use ieee.std_logic_1164.all; entity counter_tb is end entity; architecture behavioral of counter_tb is signal clk, count_en, f0, f1 : std_logic := '0'; begin dut: entity work.counter port map(clk, count_en, f0, f1); clk <= not clk after 10 ns; count_proc: process begin count_en <= '0'; wait for 99 ns; wait until rising_edge(clk); count_en <= '1'; wait until rising_edge(clk); count_en <= '0'; wait; end process; end architecture;，则x的值不会立即更改：它只会排队。直到下一个增量周期才会处理所有实际分配，这将在一段时间延迟之后发生：在这种情况下，在完全评估过程之后，因为没有x <= y;语句。在测试平台中，您可以在一个进程中拥有多个x语句，这将导致时间延迟，从而触发分配。

更详细：在应用程序中。说：

wait

模拟结束后（1-2个delta周期）wait将为entity foo is end entity; architecture bar of foo is signal x : bit := '1'; signal y : bit; begin process begin x <= '0'; y <= x; wait; end process; end architecture;而x将为'0'，因为y已分配给{在下一个delta周期之前不会发生{1}}，在这种情况下，这将发生在无限'1'语句中，因为引入了时间延迟。

VHDL在时钟边沿使用输入值

1 个答案:

编辑：