目标是执行至少一百次迭代的奇异函数。最终目标是完全达到门级。我无法理解，所以我试图让常规代码工作。但我无法让这台状态机循环两次。由于测试结果，有很多随机注释代码。我需要让计数器/比较器以某种方式工作。返回状态零并恢复该过程。下面是我用来尝试测试它的主要代码和测试平台。我只能让第一次迭代工作。但不能得到任何其他东西。
如有任何帮助，我们将不胜感激。谢谢。
//Verilog module for Project
`timescale 1ns/1ps
module Project1(
clk, rst, start,
x_in, u_in, y_in,
x_out, u_out, y_out
);
//List the inputs and their sizes
input clk, rst, start;
input [7:0] x_in, u_in, y_in;
//List the outputs and their sizes
output integer x_out, u_out, y_out;
//Internal variables
// integer [7:0] rx4, rx2, rdx, r3, rudx, r3ux4_yx4, rux4_x4y;
// integer [7:0] ru_y;
reg [7:0] min1, min2;
reg [15:0] tempmult;
reg [7:0] ain1, ain2;
reg [8:0] tempadd;
integer x_i, u_i, y_i;
integer rx4, rx2, rdx, r3, rudx, r3ux4_yx4, rux4_x4y;
integer ru_y;
integer count = 0;
//List of Wires
// Declare state register and parameter
reg [3:0] state;
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4, S5 = 5, S6 = 6;
//Instantiate Modules ----------------------------------------------------
//Multiplier
lpmmult multiply(
.clock(clk),
.dataa(min1),
.datab(min2),
.result(mout));
//Adder
adders adderss(
.clock(clk),
.data0x(ain1),
.data1x(ain2),
.result(aout));
// always block
always @ (posedge clk or posedge rst) begin:FSM_ST
// Determine the next state
if (rst) begin
rdx = 1;
r3 = 6;
x_i <= x_in;
u_i <= u_in;
y_i <= y_in;
state <= S0;
end else if(start) begin //End If Start else
case (state)
S0: begin
// Multiplying using instantiated module
// min1 <= x_i;
// min2 <= x_i;
// tempmult <= mout;
// rx2 <= tempmult[15:8];
// // Adding using instantiated module
// ain1 <=x_i;
// ain1 <=rdx;
// tempadd <= aout;
// if (tempadd[8] == 1) begin
// x_out <= tempadd[8:1];
// end else begin
// x_out <= tempadd[7:0];
// end
rx2 <= x_i*x_i; //Multiplying using regular way
x_out <= x_i+rdx; //Adding using regular way
if (count < 10) begin
count = count + 1;
state = S1;
$display("Time %2d: x_out %1d is %2d", $time, x_out, y_out);
#10;
end
else begin
state <= S1;
end
end// End State0
S1: begin
rx4 <= rx2*rx2;
ru_y <= u_i+y_i;
// Multiplying using instantiated module
// min1 <= rx2;
// min2 <= rx2;
// tempmult <= mout;
// rx4 <= tempmult[15:8];
//
// Adding using instantiated module
// ain1 <=u_i;
// ain1 <=y_i;
// tempadd <= aout;
// if (tempadd[8] == 1) begin
// ru_y <= tempadd[8:1];
// end else begin
// ru_y <= tempadd[7:0];
// end
state <= S2;
end// End State1
S2: begin
rux4_x4y <= rx4*ru_y;
// min1 <= rx4;
// min2 <= ru_y;
// tempmult <= mout;
// rux4_x4y <= tempmult[15:8];
state <= S3;
end// End State2
S3: begin
r3ux4_yx4 <= rux4_x4y*r3;
// min1 <= rux4_x4y;
// min2 <= r3;
// tempmult <= mout;
// r3ux4_yx4 <= tempmult[15:8];
state <= S4;
end// End State3
S4: begin
rudx <= u_i*rdx;
u_out <= r3ux4_yx4+u_i;
// min1 <= u_i;
// min2 <= rdx;
// tempmult <= mout;
// rudx <= tempmult[15:8];
//
// // Adding using instantiated module
// ain1 <=r3ux4_yx4;
// ain1 <=u_i;
// tempadd <= aout;
// if (tempadd[8] == 1) begin
// u_out <= tempadd[8:1];
// end else begin
// u_out <= tempadd[7:0];
// end
state <= S5;
end// End State4
S5: begin
y_out <= rudx + y_i;
// Adding using instantiated module
// ain1 <=rudx;
// ain1 <=y_i;
// tempadd <= aout;
// if (tempadd[8] == 1) begin
// y_out <= tempadd[8:1];
// end else begin
// y_out <= tempadd[7:0];
// end
state <= S6;
end// End State5
S6: begin
//Write output code Here
if (start) begin
state = S0;
end
// if (count < 10) begin
// count = count + 1;
// state = S0;
// $display("Time %2d: x_out %1d is %2d", $time, x_out, y_out);
// #10;
// end
end// End State6
default:
state <= S6;
endcase
end // End Else
end// End always module
// always @ (posedge clk) begin:FSM_S
// if (count < 10) begin
// count = count + 1;
// //state = S0;
// $display("Time %2d: x_out %1d is %2d", $time, x_out, y_out);
// #10;
// end
// end
endmodule
[/ CODE]
//Verilog testbench module for Project
`timescale 1ns/1ps
module Project1_tb;
reg clk, rst, start; //reset = active HIGH
integer x_in, u_in, y_in;
wire [7:0] x_out, u_out, y_out;
Project1 uut(
.clk(clk), .rst(rst), .start(start),
.x_in(x_in), .u_in(u_in), .y_in(y_in),
.x_out(x_out), .u_out(u_out), .y_out(y_out)
);
initial begin
clk = 0;
forever #50 clk = ~clk;
end
initial begin
#1000;
start = 0;
x_in = 8'b00000010;
u_in = 8'b00000100;
y_in = 8'b00000100;
rst = 1;
#1000;
rst = 0;
#1000;
start = 1;
#1000;
start = 0;
#1000;
rst = 1;
#1000;
rst = 0;
#1000;
start = 1;
#50000;
end
endmodule
答案 0 :(得分：0)
如果你至少会描述你尝试做什么，那会有所帮助。看起来像重复的加倍。
我刚刚“扫描”了您的代码。您正在混合阻止和非阻塞分配。在一个时钟部分（总是@posedge ...）你只使用非阻塞分配（有一些例外，但你可能还没有为那些做好准备）。先修复它们然后重新尝试。
此外，您在时钟部分的第一个顶级“if”是“if（start）”。这不是一个启动。除非“开始”很高，否则什么都不会运行。
一如既往的一些提示：
处理你的评论。 “//声明状态寄存器和参数”类型的注释是无用的。它就像：
a=a+1 // Adding 1 to 'a'
同时，您尚未在文件顶部声明模块应该执行的操作。名称Project1也不是很具描述性。