Verilog十六进制显示和始终阻止混乱

Question

在这个verilog代码中，我试图根据我所处的状态输出十六进制消息和led灯。状态0是四个字母＆＃39; ABCD＆＃39;。状态1是＆＃39; S_01＆＃39;，状态2是＆＃39; S_02＆＃39;，状态3是＆＃39; S_03＆＃39;，状态4是＆＃39; S_04＆＃39;。

在我的下面的代码中，我相信我推断了我的LED_SW的锁存器，但我不确定。此外，当我的代码编译时，我无法模拟没有错误和警告。主要是错误和警告，指的是我在第319-322行的陈述，指出端口＆＃39; HexSeg＆＃39;＆＃39;有非法输出或端口连接。我很感激有关如何修复代码的任何提示或想法。

对于这个问题，我认为可以忽略第一个ASCII27Seg模块，也可以忽略FSMtestOne模块。此外，没有必要看我的去抖模块。我特别关注我的FSM模块中的代码。

module ASCII27Seg(input [7:0] AsciiCode, output reg [6:0] HexSeg);
  always @ (*) begin
    HexSeg = 8'd0;
    $display("AsciiCode %b", AsciiCode);
    case (AsciiCode)
      // A
      8'h41 : HexSeg[3] = 1;
      // a
      8'h61 : HexSeg[3] = 1;
      // B
      8'h42 : begin
          HexSeg[0] = 1; HexSeg[1]=1;
      end
      // b
      8'h62 : begin
         HexSeg[0] = 1; HexSeg[1]=1;
      end
      // C
      8'h43 : begin
         HexSeg[1] = 1; HexSeg[2] = 1; HexSeg[6] = 1;
      end
      // c
      8'h63 : begin
         HexSeg[1] = 1; HexSeg[2] = 1; HexSeg[6] = 1;
      end
      // D
      8'h44 : HexSeg[6] = 1;
      // d
      8'h64 : begin
        HexSeg[0] = 1; HexSeg[5] = 1;
      end
      // E
      8'h45 : begin
        HexSeg[1] = 1; HexSeg[2] = 1;
      end
      // e
      8'h65 : begin
        HexSeg[1] = 1; HexSeg[2] = 1;
      end
      // F
      8'h46 : begin
        HexSeg[1] = 1; HexSeg[2] = 1; HexSeg[3] = 1;
      end
      // f
      8'h66 : begin
        HexSeg[1] = 1; HexSeg[2] = 1; HexSeg[3] = 1;
      end
      // G
      8'h47 : HexSeg[4] = 1;
      // g
      8'h67 : HexSeg[4] = 1;
      // H
      8'h48 : begin
        HexSeg[0] = 1; HexSeg[3] = 1;
      end
      // h
      8'h68 : begin
        HexSeg[0] = 1; HexSeg[3] = 1;
      end
      // I
      8'h49 : begin
        HexSeg[0] = 1; HexSeg[1] = 1; HexSeg[2] = 1; HexSeg[3] = 1; HexSeg[6] = 1;
      end
      // i
      8'h69 : begin
        HexSeg[0] = 1; HexSeg[1] = 1; HexSeg[2] = 1; HexSeg[3] = 1; HexSeg[6] = 1;
      end
      // J
      8'h4a : begin
        HexSeg[0] = 1; HexSeg[5] = 1; HexSeg[6] = 1;
      end
      // j
      8'h6a : begin
        HexSeg[0] = 1; HexSeg[5] = 1; HexSeg[6] = 1;
      end
      // K
      8'h4b : begin
        HexSeg[0] = 1; HexSeg[3] = 1;
      end
      // k
      8'h6b : begin
        HexSeg[0] = 1; HexSeg[3] = 1;
      end
      // L
      8'h4c : begin
        HexSeg[0] = 1; HexSeg[1] = 1; HexSeg[2] = 1; HexSeg[6] = 1;
      end
      // l
      8'h6c : begin
        HexSeg[0] = 1; HexSeg[1] = 1; HexSeg[2] = 1; HexSeg[6] = 1;
      end
      // M
      8'h4d : begin
        HexSeg[1] = 1; HexSeg[3] = 1; HexSeg[5] = 1; HexSeg[6] = 1;
      end
      // m
      8'h6d : begin
        HexSeg[1] = 1; HexSeg[3] = 1; HexSeg[5] = 1; HexSeg[6] = 1;
      end
      // N
      8'h4e : begin
        HexSeg[0] = 1; HexSeg[1] = 1; HexSeg[3] = 1; HexSeg[5] = 1;
      end
      // n
      8'h6e : begin
        HexSeg[0] = 1; HexSeg[1] = 1; HexSeg[3] = 1; HexSeg[5] = 1;
      end
      // O
      8'h4f : HexSeg[6] = 1;
      // o
      8'h6f : HexSeg[6] = 1;
      // P
      8'h50 : begin
        HexSeg[2] = 1; HexSeg[3] = 1;
      end
      // p
      8'h70 : begin
        HexSeg[2] = 1; HexSeg[3] = 1;
      end
      // Q
      8'h51 : begin
        HexSeg[3] = 1; HexSeg[4] = 1;
      end
      // q
      8'h71 : begin
        HexSeg[3] = 1; HexSeg[4] = 1;
      end
      // R
      8'h52 : begin
        HexSeg[0] = 1; HexSeg[1] = 1; HexSeg[2] = 1; HexSeg[3] = 1; HexSeg[5] = 1;
      end
      // r
      8'h72 : begin
        HexSeg[0] = 1; HexSeg[1] = 1; HexSeg[2] = 1; HexSeg[3] = 1; HexSeg[5] = 1;
      end
      // S
      8'h53 : begin
        HexSeg[1] = 1; HexSeg[4] = 1;
      end
      // s
      8'h73 : begin
        HexSeg[1] = 1; HexSeg[4] = 1;
      end
      // T
      8'h54 : begin
        HexSeg[0] = 1; HexSeg[1] = 1; HexSeg[2] = 1;
      end
      // t
      8'h74 : begin
        HexSeg[0] = 1; HexSeg[1] = 1; HexSeg[2] = 1;
      end
      // U
      8'h55 : begin
        HexSeg[0] = 1; HexSeg[6] = 1;
      end
      // u
      8'h75 : begin
        HexSeg[0] = 1; HexSeg[6] = 1;
      end
      // V
      8'h56 : begin
         HexSeg[0] = 1; HexSeg[1] = 1; HexSeg[5] = 1; HexSeg[6] = 1;
      end
      // v
      8'h76 : begin
         HexSeg[0] = 1; HexSeg[1] = 1; HexSeg[5] = 1; HexSeg[6] = 1;
      end
      // W
      8'h57 : begin
        HexSeg[0] = 1; HexSeg[2] = 1; HexSeg[4] = 1; HexSeg[6] = 1;
      end
      // w
      8'h77 : begin
        HexSeg[0] = 1; HexSeg[2] = 1; HexSeg[4] = 1; HexSeg[6] = 1;
      end
      // X
      8'h58 : begin
        HexSeg[0] = 1; HexSeg[3] = 1;
      end
      // x
      8'h78 : begin
        HexSeg[0] = 1; HexSeg[3] = 1;
      end
      // Y
      8'h59 : begin
        HexSeg[0] = 1; HexSeg[4] = 1;
      end
      // y
      8'h79 : begin
        HexSeg[0] = 1; HexSeg[4] = 1;
      end
      // Z
      8'h5A : begin
        HexSeg[2] = 1; HexSeg[5] = 1;
      end
      // z
      8'h7A : begin
        HexSeg[2] = 1; HexSeg[5] = 1;

      end
      // _
      8'h5F : begin
    HexSeg[0] = 1; HexSeg[1] = 1; HexSeg[2] = 1; HexSeg[4] = 1; HexSeg[5] = 1; HexSeg[6] = 1;
      end
      // number 0
      8'h30 : begin
    HexSeg[0] = 1;
      end
      // number 1
      8'h31 : begin
    HexSeg[0] = 1; HexSeg[1] = 1; HexSeg[2] = 1; HexSeg[3] = 1; HexSeg[6] = 1;
      end
      // number 2
      8'h32 : begin
    HexSeg[1] = 1; HexSeg[4] = 1;
      end
      // number 3
      8'h33 : begin
    HexSeg[1] = 1; HexSeg[2] = 1;
      end
      // number 4
      8'h34 : begin
    HexSeg[2] = 1; HexSeg[3] = 1; HexSeg[6] = 1;
      end
      // turn all the bits off by default
      default : HexSeg = 8'b11111111;    
    endcase
  end
endmodule
// FSM
module FSM(input KEY0, SW0, SW1, SW2, SW3, SW4, output reg[6:0] HEX0, HEX1, HEX2, HEX3, output reg[2:0] state, output reg[1:0] Z, output reg[4:0] LED_SW);
    reg[7:0] Message[3:0];
    reg next_state;
    always @ (posedge KEY0) begin
      case (state)
    // reset S0
        3'b000 : begin
            if (SW0) begin
                next_state <= 3'b000;
        end
            else if (SW1)
                next_state <= 3'b001;
            end
    // S1
        3'b001 : begin
            if (SW2)
                next_state <= 3'b010;
            end
    // S2
        3'b010 : begin
            if (SW3) begin
                next_state <= 3'b011;
        end
            else if (SW1)
                next_state <= 3'b010;
            end
    // S3
        3'b011 : begin
            if (SW4) begin
                next_state <= 3'b100;
        end
            else if (SW1)
                next_state <= 3'b010;
            end
    // S4
        3'b100 : begin
            if (SW1) begin
                next_state <= 3'b010;
        end
            end
      endcase
    end
    always @ (state) begin
      case (state)  
        3'b000 : begin 
            Z = 2'b00;
            LED_SW = 5'b00010;
        Message[3] = "A";
        Message[2] = "B";
        Message[1] = "C";
        Message[0] = "D";
    end
        3'b001 : begin
            Z = 2'b00;
            LED_SW = 5'b00010;
        Message[3] = "S";
        Message[2] = "_";
        Message[1] = "0";
        Message[0] = "1";
    end
        3'b010 : begin
            Z = 2'b00;
            LED_SW = 5'b00100;
        Message[3] = "S";
        Message[2] = "_";
        Message[1] = "0";
        Message[0] = "2";
    end
        3'b011 : begin
            Z = 2'b10;
            LED_SW = 5'b01000;
        Message[3] = "S";
        Message[2] = "_";
        Message[1] = "0";
        Message[0] = "3";
    end
        3'b100 : begin
            Z = 2'b11;
            LED_SW = 5'b10000;
        Message[3] = "S";
        Message[2] = "_";
        Message[1] = "0";
        Message[0] = "4";
    end
        default : Z = 2'b00;
       endcase
     end
        ASCII27Seg SevH3 (Message[3], HEX3);
        ASCII27Seg SevH2 (Message[2], HEX2);
        ASCII27Seg SevH1 (Message[1], HEX1);
        ASCII27Seg SevH0 (Message[0], HEX0);
endmodule
// test one
`timescale 1ns/1ps
module FSMtestOne();
    reg KEY0, SW0, SW1, SW2, SW3, SW4;
    wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4;
    wire [2:0] state; 
    wire [1:0] Z;
    wire [4:0] LED_SW;
    FSM testInstanceOne(KEY0, SW0, SW1, SW2, SW3, SW4, HEX0, HEX1, HEX2, HEX3, state, Z, LED_SW);
    initial begin
        KEY0 = 1'b0; SW0 = 1'b0; SW1 = 1'b0; SW2 = 1'b0; SW3 = 1'b0; SW4 = 1'b0; #5;
        $display("KEY0 = %d, SW0 = %d, SW1 = %d, SW2 = %d, SW3 = %d, SW4 = %d, HEX0 = %c, HEX1 = %c, HEX2 = %c, HEX3 = %c, state = %d, Z = %d, LED_SW = %d", KEY0, SW0, SW1, SW2, SW3, SW4, HEX0, HEX1, HEX2, HEX3, state, Z, LED_SW);
        KEY0 = 1'b1; #5;
        $display("KEY0 = %d, SW0 = %d, SW1 = %d, SW2 = %d, SW3 = %d, SW4 = %d, HEX0 = %c, HEX1 = %c, HEX2 = %c, HEX3 = %c, state = %d, Z = %d, LED_SW = %d", KEY0, SW0, SW1, SW2, SW3, SW4, HEX0, HEX1, HEX2, HEX3, state, Z, LED_SW);
        KEY0 = 1'b0; SW0 = 1'b1; SW1 = 1'b0; SW2 = 1'b0; SW3 = 1'b0; SW4 = 1'b0; #5;
        $display("KEY0 = %d, SW0 = %d, SW1 = %d, SW2 = %d, SW3 = %d, SW4 = %d, HEX0 = %c, HEX1 = %c, HEX2 = %c, HEX3 = %c, state = %d, Z = %d, LED_SW = %d", KEY0, SW0, SW1, SW2, SW3, SW4, HEX0, HEX1, HEX2, HEX3, state, Z, LED_SW);
        KEY0 = 1'b1; #5;
        $display("KEY0 = %d, SW0 = %d, SW1 = %d, SW2 = %d, SW3 = %d, SW4 = %d, HEX0 = %c, HEX1 = %c, HEX2 = %c, HEX3 = %c, state = %d, Z = %d, LED_SW = %d", KEY0, SW0, SW1, SW2, SW3, SW4, HEX0, HEX1, HEX2, HEX3, state, Z, LED_SW);
        KEY0 = 1'b0; SW0 = 1'b0; SW1 = 1'b1; SW2 = 1'b0; SW3 = 1'b0; SW4 = 1'b0; #5;
        $display("KEY0 = %d, SW0 = %d, SW1 = %d, SW2 = %d, SW3 = %d, SW4 = %d, HEX0 = %c, HEX1 = %c, HEX2 = %c, HEX3 = %c, state = %d, Z = %d, LED_SW = %d", KEY0, SW0, SW1, SW2, SW3, SW4, HEX0, HEX1, HEX2, HEX3, state, Z, LED_SW);
        KEY0 = 1'b1; #5;
        $display("KEY0 = %d, SW0 = %d, SW1 = %d, SW2 = %d, SW3 = %d, SW4 = %d, HEX0 = %c, HEX1 = %c, HEX2 = %c, HEX3 = %c, state = %d, Z = %d, LED_SW = %d", KEY0, SW0, SW1, SW2, SW3, SW4, HEX0, HEX1, HEX2, HEX3, state, Z, LED_SW);
        KEY0 = 1'b0; SW0 = 1'b0; SW1 = 1'b0; SW2 = 1'b1; SW3 = 1'b0; SW4 = 1'b0; #5;
        $display("KEY0 = %d, SW0 = %d, SW1 = %d, SW2 = %d, SW3 = %d, SW4 = %d, HEX0 = %c, HEX1 = %c, HEX2 = %c, HEX3 = %c, state = %d, Z = %d, LED_SW = %d", KEY0, SW0, SW1, SW2, SW3, SW4, HEX0, HEX1, HEX2, HEX3, state, Z, LED_SW);
        KEY0 = 1'b1; #5;
        $display("KEY0 = %d, SW0 = %d, SW1 = %d, SW2 = %d, SW3 = %d, SW4 = %d, HEX0 = %c, HEX1 = %c, HEX2 = %c, HEX3 = %c, state = %d, Z = %d, LED_SW = %d", KEY0, SW0, SW1, SW2, SW3, SW4, HEX0, HEX1, HEX2, HEX3, state, Z, LED_SW);
        KEY0 = 1'b0; SW0 = 1'b0; SW1 = 1'b0; SW2 = 1'b0; SW3 = 1'b1; SW4 = 1'b0; #5;
        $display("KEY0 = %d, SW0 = %d, SW1 = %d, SW2 = %d, SW3 = %d, SW4 = %d, HEX0 = %c, HEX1 = %c, HEX2 = %c, HEX3 = %c, state = %d, Z = %d, LED_SW = %d", KEY0, SW0, SW1, SW2, SW3, SW4, HEX0, HEX1, HEX2, HEX3, state, Z, LED_SW);
        KEY0 = 1'b1; #5;
        $display("KEY0 = %d, SW0 = %d, SW1 = %d, SW2 = %d, SW3 = %d, SW4 = %d, HEX0 = %c, HEX1 = %c, HEX2 = %c, HEX3 = %c, state = %d, Z = %d, LED_SW = %d", KEY0, SW0, SW1, SW2, SW3, SW4, HEX0, HEX1, HEX2, HEX3, state, Z, LED_SW);
        KEY0 = 1'b0; SW0 = 1'b0; SW1 = 1'b0; SW2 = 1'b1; SW3 = 1'b0; SW4 = 1'b0; #5;
        $display("KEY0 = %d, SW0 = %d, SW1 = %d, SW2 = %d, SW3 = %d, SW4 = %d, HEX0 = %c, HEX1 = %c, HEX2 = %c, HEX3 = %c, state = %d, Z = %d, LED_SW = %d", KEY0, SW0, SW1, SW2, SW3, SW4, HEX0, HEX1, HEX2, HEX3, state, Z, LED_SW);
        KEY0 = 1'b1; #5;
        $display("KEY0 = %d, SW0 = %d, SW1 = %d, SW2 = %d, SW3 = %d, SW4 = %d, HEX0 = %c, HEX1 = %c, HEX2 = %c, HEX3 = %c, state = %d, Z = %d, LED_SW = %d", KEY0, SW0, SW1, SW2, SW3, SW4, HEX0, HEX1, HEX2, HEX3, state, Z, LED_SW);
        KEY0 = 1'b0; SW0 = 1'b1; SW1 = 1'b0; SW2 = 1'b0; SW3 = 1'b0; SW4 = 1'b0; #5;
        $display("KEY0 = %d, SW0 = %d, SW1 = %d, SW2 = %d, SW3 = %d, SW4 = %d, HEX0 = %c, HEX1 = %c, HEX2 = %c, HEX3 = %c, state = %d, Z = %d, LED_SW = %d", KEY0, SW0, SW1, SW2, SW3, SW4, HEX0, HEX1, HEX2, HEX3, state, Z, LED_SW);
    end
endmodule

// debounce module
module debounce3 #(parameter cntSize = 8)(input reset, input Clk, input PB, output reg pulse);
reg[cntSize-1:0] cnt;
always @ (posedge Clk)
    if (reset)
        cnt <= {cntSize{1'b0}};
    else
        begin
            cnt <= {cnt[cntSize-2:0], PB};
            if ( &cnt ) pulse <= 1'b1;
            else if (~|cnt) pulse <= 1'b0;
        end
endmodule

Answer 1

在第319-322行中，输出变量HEX0，HEX等属于reg类型。它们应该是电线：

FSM(
   input KEY0, SW0, SW1, SW2, SW3, SW4, 
   output [6:0] HEX0, HEX1, HEX2, HEX3, // << No reg.

此外，对于代码来说，如果您更容易阅读以发现错误，它会有所帮助。有一些编码技巧，例如：

begin
   HexSeg[0] = 1; HexSeg[1]=1;
end
can be written as:
{HexSeg[0],HexSeg[1]}=2'b11;

然后

8'h42 : begin
    HexSeg[0] = 1; HexSeg[1]=1;
end
// b
8'h62 : begin
   HexSeg[0] = 1; HexSeg[1]=1;
end
8'h43 : begin
    HexSeg[1] = 1; HexSeg[2] = 1; HexSeg[6] = 1;
end
// c
8'h63 : begin
   HexSeg[1] = 1; HexSeg[2] = 1; HexSeg[6] = 1;
end

可以写成：

8'h42, 8'h62 : {HexSeg[0],HexSeg[1]}=2'b11;
8'h43, 8'h63 : {HexSeg[1],HexSeg[2],HexSeg[6]} = 3'b111;

我个人更喜欢：

8'h41, 8'h61 : HexSeg = 8'b00001000; // A,a
8'h42, 8'h62 : HexSeg = 8'b00000011; // B,b
8'h43, 8'h63 : HexSeg = 8'b01000110; // C,c
8'h44, 8'h64 : HexSeg = 8'b00100001; // D,d
8'h45, 8'h65 : HexSeg = 8'b00000110; // E,e
etc.