使用`typedef`时:在哪里放置数组指示?

时间:2018-01-31 14:16:21

标签: system-verilog

使用typedef声明userdefine类型时,ModelSim接受这两种形式:

typedef logic logic_7_0_t [7:0];
typedef logic [7:0] logic_7_0_t;

但是,如果基于real类型执行类似操作,则第二种格式会失败:

typedef real real_3_0_t [3:0];
typedef real [3:0] real_3_0_t;  // Syntax error by ModelSim

放置数组指示的位置,以及logicreal之间差异的原因?

1 个答案:

答案 0 :(得分:0)

基于对重复答案的引用,我的结论是:

typedef logic logic_7_0_t [7:0];  // Unpacked array of logic, which is OK
typedef logic [7:0] logic_7_0_t;  // Packed array of logic, which is OK

typedef real real_3_0_t [3:0];    // Unpacked array or real, which is OK
typedef real [3:0] real_3_0_t;    // Would be packed array of real, which is not illegal