尝试构建64位8:1 MUX时出错

时间:2018-01-26 22:30:10

标签: system-verilog modelsim quartus test-bench

通过级联MUX我创建了一个8:1 MUX,我需要它输入8个不同的64位值,然后MUX可以从中选择输出64位值。尝试在ModelSIm中运行我的测试平台时出现此错误:数组连接类型'wire [63:0] $ [7:0]'与端口(A)的'wire [7:0]'不兼容:不能混合打包和解包类型。

module control_MUX (control, holdVal, out);
input [2:0] control;
input [63:0] holdVal [7:0];
output [63:0] out;

multi8 ctrlMUX (out, control, holdVal [7:0]);

endmodule 

module control_MUX_testbench();
wire [63:0]out;
reg [63:0] holdVal [7:0];
reg [2:0] control;


control_MUX dut (control, holdVal, out);

initial begin   

 holdVal[0] = 64'd0;
 holdVal[1] = 64'd1;
 holdVal[2] = 64'd2;
 holdVal[3] = 64'd3;
 holdVal[4] = 64'd4;
 holdVal[5] = 64'd5;
 holdVal[6] = 64'd6;
 holdVal[7] = 64'd7;    

      control = 3'b000; #10;
      control = 3'b001; #10;
      control = 3'b010;     #10;
      control = 3'b011;     #10;
      control = 3'b100;     #10;
      control = 3'b101;     #10;    
      control = 3'b110;     #10;
      control = 3'b111;     #10;

    end
endmodule 


// 8x3 multiplexer 
// A is the 8 bit input and select is a 3 bit input
module multi8 (out, select, A);
    output [63:0] out;
    input [7:0] A;
    input [2:0] select;
    wire mux3, mux4;

    multi4 muxC (mux3, select[1:0], A[3:0]);
    multi4 muxD (mux4, select[1:0], A[7:4]);
    multi2 final8 (out, select[2], mux3, mux4);
endmodule

1 个答案:

答案 0 :(得分:0)

multi8模块存在问题。端口A声明为

input [7:0] A;

虽然您将模块实例化为

input [63:0] holdVal [7:0];
multi8 ctrlMUX (out, control, holdVal [7:0]);

在这种情况下,您尝试将整个8元素解压缩的64位元素数组映射到单个8位元素中。这绝对是一个错误。

所以,你需要在那里找出你的尺寸。