Question

我用VHDL编写了这段代码：

library IEEE ;
use IEEE.STD_LOGIC_1164.all ;


entity encoder is 
port(
    x : in std_logic_vector (7 downto 0);
  en : in std_logic ;
  y : out std_logic_vector (2 downto 0));
end encoder;

architecture enc_arch of encoder is 
begin

  process(en,x) 
  begin 
    if (en ='0') then
      y<= "000";
    else 
      y<= "001" when (x = '00000010') else
          '010' when (x = '00000100') else 
          '011' when (x = '00001000') else 
          '100' when (x = '00010000') else 
          '101' when (x = '00100000') else 
          '110' when (x = '01000000') else 
          '111' when (x = '10000000') else
          '000' ;
    end if ;
  end process ;

end enc_arch;

错误是：

vhd（20）：near“'”：语法错误

vhd（30）：VHDL编译器退出

任何人都可以帮我解决这些问题吗？

Answer 1

(x = '10000000')（和所有类似的行）应该有＆＃39; ＆＃39;改为＆＃34; ＆＃34;：(x = "10000000")

这是因为单引号用于std_logic，而双引号用于std_logic_vector。

此外：

{library IEEE ;应该是：library IEEE ;

和end enc_arch;}应为end enc_arch;

Answer 2

顺序正文中的条件语句（[when ... else] statement）仅在VHDL 1076-2008中受支持。

如果您不使用此版本的VHDL，则可以在顺序正文中使用case语句。还会在向量中将'更改为"。您的代码的Currect代码是：

library IEEE ;
use IEEE.STD_LOGIC_1164.all ;

entity encoder is 
  port(
    x  : in  std_logic_vector (7 downto 0);
    en : in  std_logic ;
    y  : out std_logic_vector (2 downto 0));
end encoder;

architecture enc_arch of encoder is 
begin

  process(en,x) 
  begin 
    if (en ='0') then
      y<= "000";
    else 
     case x is 
        when "00000010" =>
            y<= "001" ;
        when "00000100" =>
            y<= "010" ;
        when "00001000" =>
            y<= "011" ;
        when "00010000" =>
            y<= "100" ;
        when "00100000" =>
            y<= "101" ;
        when "01000000" =>
            y<= "110" ;
        when "10000000" =>
            y<= "111" ;
        when others =>
            y<= "111" ;
     end case ;
    end if ;
  end process ;

end enc_arch;

“'”附近：语法错误

2 个答案: