我们可以在SystemC中将两个Hierarchical通道与一个Module连接吗？

Question

我们可以在SystemC中将两个分层通道与一个模块连接吗？

我已经制作了频道，以便One Module＆＃34; MACC0＆＃34;可以连接到另外两个模块＆＃34; Wcache＆＃34;和＃34; ImageCache＆＃34;通过端口接口连接，但我遇到了错误。

//------------------------------------------------------------------------
#include "systemc.h"
#include "Memory.h"
#include "ImageCache.h"
#include "Wcache0.h"
//#include "Wcache1.h"
//#include "Wcache2.h"
//#include "Wcache3.h"
#include "MACC0.h"
//#include "MACC1.h"
//#include "MACC2.h"
//#include "MACC3.h"
#include "Ocache0.h"
//#include "Ocache1.h"
//#include "Ocache2.h"
//#include "Ocache3.h"
#include "Mux.h"
#include "Channel.h"
#include "Channel2.h"

int sc_main(int argc, char* argv[])
{
// -----------------Signal declarations-----------------------------
    sc_signal<int> state_M;
    sc_signal<bool> Mem_inp1;
    sc_signal<bool> Mem_out1;
    sc_signal<bool> Mem_out2;
    sc_signal<int>  Imgcache_out1;
    sc_signal<int>  Imgcache_out2;

    sc_signal<int>  W1M1;
    sc_signal<int>  W1M2;

    sc_signal<int>  M1O1;
    sc_signal<int>  O1M;

    sc_signal<int>  Mux_out;
    sc_signal<int>  Mem_inp2;

//---------------Instantiations-----------------------------------
    Memory     Memory("m1");
    //ImageCache ImgCache("m2");
    //Wcache0    Wcache1("m3");
    //MACC0      MACC1("m7");

    ImageCache  *ImgCache;
    Wcache0     *Wcache1;
    MACC0       *MACC1;
    Channel     *H_channel1;
    Channel2    *H_channel2;

    ImgCache = new ImageCache("m2");
    Wcache1  = new Wcache0("m3");
    MACC1    = new MACC0("m4");
    H_channel1  = new Channel("m5");
    H_channel2  = new Channel2("m6");

    ImageCache ImgCache1("m2");
    Wcache0    Wcache("m3");
    MACC0       MACC2("m7");
    Ocache0    Ocache1("m11");
    Mux        Mux("m15");

//---------- Connection of Different Modules------------------------------
    Memory.Mem_in(Mem_inp1);
    Mem_inp1.write(1);
    Memory.Mem_out1(Mem_out1);  // Memory
    Memory.Mem_out2(Mem_out2);  // Memory
    Memory.state_out(state_M);  // Memory
    ImgCache1.input_1(Mem_out2); // ImageCache
    //ImgCache.output_1(Imgcache_out1);// Image Cache
    MACC2.state(state_M);
//--------------------PORTS CONNECTIONS----------------------------------

    ImgCache->write_port(*H_channel1);   // from Image Cache to MÁCC0
    MACC1->read_port(*H_channel1);

    Wcache1->write_port1(*H_channel2);   // from Weight Cache to MÁCC0
    MACC1->read_port1(*H_channel2);

//-----------------------------------------------------------------------
//---------------Memory Output sig_1 to all the Inputs of the Weight Cache-----
    Wcache.inp_0(Mem_out1); // Wcache0
    //Wcache2.inp_0(Mem_out1); // Wcache1
    //Wcache3.inp_0(Mem_out1); // Wcache2
    //Wcache4.inp_0(Mem_out1); // Wcache3
//-----------Weight Cache Outputs to all the Inputs of the MACCs------------
    //Wcache1.out_1(W1M1); 
    //MACC1.inp_a(W1M1); 



    /*
    Wcache2.out_0(W2M2); // Wcache1
    MACC2.inp_0(W2M2); // MACC1

    Wcache3.out_0(W3M3); // Wcache2
    MACC3.inp_0(W3M3); // MACC2

    Wcache4.out_0(W4M4); // Wcache3
    MACC4.inp_0(W4M4); // MACC3
    */
//-------------Imagecache Output to all the Input of the MACCs------------
    //MACC1.inp_1(Imgcache_out1); // MACC0
    //MACC1.inp_2(Imgcache_out2); // MACC0

    //MACC2.inp_1(Imgcache_out); // MACC1
    //MACC3.inp_1(Imgcache_out); // MACC2
    //MACC4.inp_1(Imgcache_out); // MACC3

//------------MACCs outputs towards the Output Caches-------------------

    MACC2.out_0(M1O1); // MACC0
    Ocache1.inp_0(M1O1); //OCache0
    /*
    MACC2.out_0(M2O2); // MACC1
    Ocache2.inp_0(M2O2); // Ocache1

    MACC3.out_0(M3O3); // MACC2
    Ocache3.inp_0(M3O3); //Ocache2

    MACC4.out_0(M4O4); // MACC3
    Ocache4.inp_0(M4O4); // Ocache3
    */
//---------Output Caches Output towards the Mux--------------------

    Ocache1.out_0(O1M); //OCache0
    Mux.ocache_0(O1M); // Mux
    /*
    Ocache2.out_0(O2M); //OCache1
    Mux.ocache_1(O2M); // Mux

    Ocache3.out_0(O3M); //OCache2
    Mux.ocache_2(O3M); // Mux

    Ocache4.out_0(O4M); //OCache3
    Mux.ocache_3(O4M); // Mux
    */

//--------Mux Output---------------------------------------------
    Mux.selection(Mux_out);
    Mux_out.write(0);
    Mux.muxout(Mem_inp2); // Mux

    // -------Mux output Written back to memory-------------------
    Memory.Mem_in1(Mem_inp2);  // Memory
    Mem_inp2.write(Mem_inp2);

    // SIMULATION STARTING 
    sc_start(5000, SC_NS); // Execution of Simulation



    getchar();

    return(0);

}