在RTL编码期间,哪些项目被考虑作为寄存器?

时间:2017-12-14 10:30:11

标签: verilog register-transfer-level

模块a( 输入b; 输出c;) //在计划框图中选择注册 //例如:屏蔽中断,超时寄存器 endmodule

1 个答案:

答案 0 :(得分:0)

查看这2个反转1位输入的简单模块:

  1. 在这一个中,输入和输出之间没有寄存器

    <script src="https://ajax.googleapis.com/ajax/libs/jquery/2.1.1/jquery.min.js"></script>
    <script src="https://netdna.bootstrapcdn.com/bootstrap/3.3.7/js/bootstrap.min.js"></script>
    <link rel="stylesheet" href="https://netdna.bootstrapcdn.com/bootstrap/3.3.7/css/bootstrap.min.css">
    <table class="table">
      <tr>
        <td class="star-ratings">
          <div class="crop" title="rating">
            <div id="star">
              <span class="glyphicon glyphicon-star-empty"></span>
              <span class="glyphicon glyphicon-star-empty"></span>
              <span class="glyphicon glyphicon-star-empty"></span>
              <span class="glyphicon glyphicon-star-empty"></span>
              <span class="glyphicon glyphicon-star-empty"></span>
            </div>
          </div>
        </td>
      </tr>
    </table>
  2. 下面是一张显示rtl代码翻译的图片:

    simple inverter

    1. 但是在反相输入后的这个模块中,该模块将其注册,并在时钟信号的上升沿将其作为输出:

      module inv(in, out);
          input  in;
          output out;
          assign out=~in; 
      endmodule
      
    2. 及以下是一张显示rtl代码翻译的图片:

      simple inverter that register the input