Verilog内存模块

Question

我是verilog的新手，我正在尝试编写一个内存模块来写入和读取文件，但是从文件读取时出现问题..

我写了一个data_memory作为Memort模块，然后我写了DataMemorytb作为测试平台

我写得很好但是当我读到xxxxx时，有人知道为什么吗？或者我的代码中有什么问题？

这是我的记忆模块：

module data_memory (
    input wire [31:0] addr,          // Memory Address
    input wire [31:0] write_data,    // Memory Address Contents
    input wire memwrite, memread,
    input wire clk,                  // All synchronous elements, including 
    memories, should have a clock signal
    output reg [31:0] read_data      // Output of Memory Address Contents
    );

reg [31:0] MEMO[0:1023];  // 256 words of 32-bit memory

integer i;
integer file;
initial begin
file = $fopen("C:\Users\hossa\Desktop/mem.txt");
read_data <= 0;
  for (i = 0; i < 1024; i = i + 1) begin
     MEMO[i] = 0;
     $fmonitor(file,"@%h\n%b",i,MEMO[i]);
end
end

always @(posedge clk) begin
  if (memwrite == 1'b1) begin
     MEMO[addr] <= write_data;
  end
  if (memread == 1'b1) begin
     read_data <= MEMO[addr];
     $fmonitor(file,"@%h\n%b",addr,MEMO[addr]);
     $display("%b @%h",MEMO[addr],addr);
  end
end

endmodule

和我的测试平台：

module DataMemorytb;

// Inputs
reg [31:0] addr;
reg [31:0] write_data;
reg memwrite;
reg memread;
reg clk;

// Outputs
wire [31:0] read_data;

// Instantiate the Unit Under Test (UUT)
    data_memory uut (
    .addr(addr), 
    .write_data(write_data), 
    .memwrite(memwrite), 
    .memread(memread), 
    .clk(clk), 
    .read_data(read_data)
);
always 
begin
#5 clk=~clk;
end
initial begin
        // Initialize Inputs
        addr = 2;
        write_data = 32'd54;
        memwrite = 1;
        memread = 0;
        clk=0;
        // Wait 100 ns for global reset to finish
        #5
        addr = 9;
        write_data = 16;
        memwrite = 1;
        memread = 0;
        #5
        addr = 3;
        write_data = 62;
        memwrite = 1;
        memread = 0;
        // Add stimulus here
        #5
        addr = 2;
        write_data = 50;
        memwrite = 0;
        memread = 1;
        #5
        addr = 9;
        write_data = 0;
        memwrite = 0;
        memread = 1;
        #5
        addr = 3;
        memread=1;
       #5
        memread=0;
    end
endmodule